公开(公告)号：US10037271B1

公开(公告)日：2018-07-31

申请号：US13535323

申请日：2012-06-27

Applicant: Brian M. Andersen

Inventor： Brian M. Andersen

IPC: G06F17/00 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0868 ,  G06F12/122 ,  G06F12/123 ,  G06F12/127 ,  G06F12/128 ,  G06F16/24552 ,  G06F2212/1016 ,  G06F2212/163 ,  G06F2212/2515 ,  G06F2212/261

Abstract: A database system may include a memory device that includes a least a portion to serve as a buffer cache and an array of persistent storage devices configured to store data of a database. The database system may monitor a frequency of data value associated with a first portion of data of the database stored in the buffer cache. The database system may maintain the first portion of data in the buffer cache in response to the frequency of data value associated with the first portion of data being greater than a frequency of data value associated with at least a portion of the data of the database stored in the array of persistent storage devices.

公开(公告)号：US09971691B2

公开(公告)日：2018-05-15

申请号：US15263148

申请日：2016-09-12

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Blaise Fanning

IPC: G06F12/0846 ,  G06F12/0831 ,  G11C7/10 ,  G06F12/0811

CPC classification number: G06F12/0851 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/0864 ,  G06F2212/1016 ,  G06F2212/2515 ,  G06F2212/283 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/621 ,  G11C7/1072

Abstract: Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache entry can include a value in a metadata field indicating an interleave policy. The cache controller can selectively assign the interleave policy to be applied based on a type of data stored in the plurality of cache memories.

公开(公告)号：US09747197B2

公开(公告)日：2017-08-29

申请号：US14282912

申请日：2014-05-20

Applicant: HONEYWELL INTERNATIONAL INC.

Inventor： Thom Kreider ,  Jon Douglas Gilreath ,  Gary Warnica

IPC: G06F15/82 ,  G06F9/302 ,  G06F12/02 ,  G06F9/30 ,  G06F9/44 ,  G06F9/54

CPC classification number: G06F12/023 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/4494 ,  G06F9/544 ,  G06F9/547 ,  G06F15/82 ,  G06F2212/251 ,  G06F2212/2515 ,  G06F2212/6042

Abstract: A method for using an access triggered architecture for a computer implemented application is provided. The method receives a set of data at a designated functional block associated with a system memory location; performs an operation at the designated functional block, using the set of data, to generate a result, wherein the operation is performed each time information is received at the designated functional block; and returns the generated result to the system memory location.

公开(公告)号：US20170199843A1

公开(公告)日：2017-07-13

申请号：US15470585

申请日：2017-03-27

Applicant: FISHER-ROSEMOUNT SYSTEMS, INC.

Inventor： Mark J. Nixon ,  Terrence L. Blevins ,  Daniel D. Christensen ,  Paul Richard Muston ,  Ken J. Beoughter

IPC: G06F15/173 ,  G05B13/02 ,  G06F9/54 ,  G05B19/418

CPC classification number: G06F15/17331 ,  G05B13/0265 ,  G05B19/4185 ,  G05B2219/31211 ,  G05B2219/31324 ,  G06F9/54 ,  G06F15/173 ,  G06F2212/2515 ,  Y02P90/18

Abstract: A device supporting big data in a process plant includes an interface to a communications network, a cache configured to store data observed by the device, and a multi-processing element processor to cause the data to be cached and transmitted (e.g., streamed) for historization at a unitary, logical centralized data storage area. The data storage area stores multiple types of process control or plant data using a common format. The device time-stamps the cached data, and, in some cases, all data that is generated or created by or received at the device may be cached and/or streamed. The device may be a field device, a controller, an input/output device, a network management device, a user interface device, or a historian device, and the device may be a node of a network supporting big data in the process plant. Multiple devices in the network may support layered or leveled caching of data.

公开(公告)号：US20170083444A1

公开(公告)日：2017-03-23

申请号：US14862030

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kapil Dev ,  Mitesh R. Meswani ,  David A. Roberts ,  Yasuko Eckert ,  Indrani Paul ,  John Kalamatianos

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0871 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/121 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/2515 ,  G06F2212/502 ,  G06F2212/601

Abstract: A cache controller to configure a portion of a first memory as cache for a second memory responsive to an indicator of locality of memory access requests to the second memory. The indicator of locality determines a probability that a location of a memory access request to the second memory is predictable based upon at least one previous memory access request. The cache controller may determine a size of the cache based on a value of the indicator of locality or modify the size of the cache in response to changes in the value of the indicator of locality.

公开(公告)号：US09356602B1

公开(公告)日：2016-05-31

申请号：US14712744

申请日：2015-05-14

Applicant: Xilinx, Inc.

Inventor： Luis E. Bielich ,  Robert E. Nertney

IPC: H03K19/177 ,  G06F12/00 ,  H03K19/00 ,  G06F12/08 ,  G06F13/16 ,  G06F9/50 ,  G06F11/10 ,  G06F21/79

CPC classification number: H03K19/1776 ,  G06F9/5016 ,  G06F11/1064 ,  G06F12/0292 ,  G06F12/0615 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/126 ,  G06F13/1694 ,  G06F21/79 ,  G06F2212/1044 ,  G06F2212/206 ,  G06F2212/2515 ,  G06F2212/6042 ,  H03K19/0008

Abstract: An approach for management of memory in a programmable integrated circuit (IC) includes configuring a memory map of the programmable IC with an association of a first subset of addresses of memory address space of the programmable IC and physical memory of the programmable IC. The memory map is further configured with an association of a second subset of addresses of the memory address space and a virtual memory block. At least a portion of a cache memory of the programmable IC is locked to the second subset of addresses.

Abstract translation: 用于管理可编程集成电路（IC）中的存储器的方法包括利用可编程IC的存储器地址空间的第一地址集群和可编程IC的物理存储器的关联来配置可编程IC的存储器映射。 存储器映射还被配置有存储器地址空间的地址的第二子集和虚拟存储器块的关联。 可编程IC的高速缓冲存储器的至少一部分被锁定到地址的第二子集。

公开(公告)号：US09134980B1

公开(公告)日：2015-09-15

申请号：US13461058

申请日：2012-05-01

Applicant: Luis Felipe Cabrera ,  Eric Jason Brandwine ,  James R. Hamilton ,  Jonathan A. Jenkins ,  Matthew D. Klein ,  Nathan Thomas ,  Pradeep Vincent

Inventor： Luis Felipe Cabrera ,  Eric Jason Brandwine ,  James R. Hamilton ,  Jonathan A. Jenkins ,  Matthew D. Klein ,  Nathan Thomas ,  Pradeep Vincent

IPC: G06F9/45 ,  G06F12/08

CPC classification number: G06F8/48 ,  G06F8/41 ,  G06F8/443 ,  G06F9/44536 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0888 ,  G06F2212/1016 ,  G06F2212/2515 ,  G06F2212/6042

Abstract: A set of techniques is described for enabling profile-driven compiler optimization based on cloud-specific information. A service provider may host applications on behalf of multiple users by providing a set of shared resources in a multi-tenant computing environment, where the resources are shared by the various applications hosted thereon. The service provider can collect runtime conditions, resource contention data and other environment-specific information of the shared resources. This gathered information can be provided a profile-driven compiler. The profile-driven compiler can use the information to recompile the source code of the application to produce an optimized version the application that is specifically tuned to run on the shared resources. The running version of the application can then be replaced by the optimized version.

Abstract translation: 描述了一组基于云特定信息启用配置文件驱动的编译器优化的技术。 服务提供商可以通过在多租户计算环境中提供一组共享资源来代表多个用户托管应用，其中资源被托管在其上的各种应用共享。 服务提供商可以收集共享资源的运行时条件，资源争用数据和其他特定于环境的信息。 这个收集的信息可以提供一个配置文件驱动的编译器。 配置文件驱动的编译器可以使用该信息来重新编译应用程序的源代码，以生成专门调优为在共享资源上运行的应用程序的优化版本。 应用程序的运行版本可以由优化版本替代。

公开(公告)号：US20150170764A1

公开(公告)日：2015-06-18

申请号：US14105443

申请日：2013-12-13

Applicant: International Business Machines Corporation

Inventor： Bhavesh D. Budhabhatti ,  Manoj Dusanapudi ,  Sairam Kamaraju ,  Varun Mallikarjunan ,  Subrat K. Panda

IPC: G11C29/10

CPC classification number: G11C29/10 ,  G06F11/263 ,  G06F12/0802 ,  G06F13/1694 ,  G06F13/385 ,  G06F2212/2515 ,  G11C7/20 ,  G11C29/26 ,  G11C2029/0409

Abstract: Using an “optimized” test case for testing hardware and/or software of a computer. The optimized test case is designed to be run on a data storage device including multiple read locations and multiple write locations. Initialization data is written, on the data storage device, only to the write locations of the data storage device. The optimized test case is run on the data storage device in a manner so that the optimized test case will only write data to each write location after that write location has had initialization data written to that write location. The optimized test case defines read locations and write locations so that, during running of the optimized test case, all read locations which are also write locations will be written by a write instruction of the test case before being read by a read instruction of the test case.

Abstract translation: 使用“优化”测试用例来测试计算机的硬件和/或软件。 优化的测试用例被设计为在包括多个读取位置和多个写入位置的数据存储设备上运行。 初始化数据在数据存储设备上写入数据存储设备的写入位置。 优化的测试用例以数据存储设备的方式运行，使得优化的测试用例仅在写入位置已将初始化数据写入该写入位置之后才将数据写入每个写入位置。 优化的测试用例定义了读取位置和写入位置，以便在优化的测试用例运行期间，所有读取位置也是写入位置将由测试用例的写入指令写入，然后通过读取测试指令进行读取 案件。

公开(公告)号：US09043538B1

公开(公告)日：2015-05-26

申请号：US14311221

申请日：2014-06-20

Applicant: Nationz Technologies Inc.

Inventor： Juan Liu ,  Fengqin Zhou ,  Mingxiang Zi

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0804 ,  G06F2212/202 ,  G06F2212/2515

Abstract: A memory system comprises a master control module, a memory control module, a nonvolatile memory and a cache, wherein the memory control module is connected with the master control module, the nonvolatile memory and the cache are respectively connected with the memory control module; and the memory control module is configured to, when the master control module sends a write command for the nonvolatile memory, store data to be written in the nonvolatile memory in the cache according to the write command, and release the cache used for storing the data to be written in the nonvolatile memory after finish of the write operation to the nonvolatile memory.

Abstract translation: 存储器系统包括主控制模块，存储器控制模块，非易失性存储器和高速缓冲存储器，其中存储器控制模块与主控模块连接，非易失性存储器和高速缓存分别与存储器控制模块连接; 并且所述存储器控制模块被配置为当所述主控制模块发送用于所述非易失性存储器的写入命令时，根据所述写入命令将要写入所述非易失性存储器的数据存储在所述高速缓存器中，并释放用于存储所述数据的所述高速缓存器 在写入操作完成之后被写入非易失性存储器中。

公开(公告)号：US08982140B2

公开(公告)日：2015-03-17

申请号：US13241745

申请日：2011-09-23

Applicant: William James Dally

Inventor： William James Dally

IPC: G06F13/28 ,  G06F15/16 ,  G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0284 ,  G06F12/08 ,  G06F12/0811 ,  G06F2212/251 ,  G06F2212/2515 ,  G06F2212/253 ,  G06F2212/302 ,  G06F2213/0038

Abstract: One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

Abstract translation: 本发明的一个实施例提出了一种用于在分层图形处理单元簇中寻址数据的技术。 基于目标数据单元所在的存储电路的位置构建分层地址。 分层地址包括指示数据单元的层次级别的级别字段和指示GPU簇内的GPU当前存储数据单元的节点标识符。 分层地址还可以包括一个或多个标识符，其指示特定层级中的哪个存储电路当前存储数据单元。 层次结构地址是基于层次域构建和解释的。 该技术有利地使得在GPU集群内执行的程序能够使用分层地址高效地访问驻留在其它GPU中的数据。