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公开(公告)号:US20240362086A1
公开(公告)日:2024-10-31
申请号:US18753989
申请日:2024-06-25
申请人: NVIDIA Corporation
CPC分类号: G06F9/54 , G06F8/311 , G06F9/4494 , G06F9/543
摘要: Apparatuses, systems, and techniques to identify a location of one or more portions of incomplete graph code. In at least one embodiment, a location of one or more portions of incomplete graph code is identified based on, for example, CUDA or other parallel computing platform code.
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公开(公告)号:US12050913B2
公开(公告)日:2024-07-30
申请号:US17080433
申请日:2020-10-26
申请人: Tenstorrent Inc.
发明人: Ljubisa Bajic , Milos Trajkovic , Ivan Hamer
CPC分类号: G06F9/30072 , G06F9/3001 , G06F9/4494 , G06N3/04 , G06N3/045 , G06N3/063 , G06N3/08
摘要: A processing core for the efficient execution of a directed graph is disclosed. The processing core includes a memory and a first and a second data tile stored in the memory. The first and second data tiles include a first and a second set of data elements stored contiguously in the memory. The processing core also includes metadata relationally stored with the first data tile in the memory. The processing core also includes an execution engine, a control unit, and an instruction. Execution of the instruction uses the execution engine, a first data element in the first set of data elements, and a second data element in the second set of data elements. The control unit conditions execution of the instruction using the metadata. A standard execution of the instruction generates a standard output. A conditional execution of the instruction operation generates a conditionally executed output.
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公开(公告)号:US11972308B2
公开(公告)日:2024-04-30
申请号:US17571335
申请日:2022-01-07
发明人: John Robert Rose , Brian Goetz
IPC分类号: G06F9/44 , G06F8/41 , G06F9/30 , G06F9/445 , G06F9/448 , G06F9/451 , G06F9/455 , G06F9/54 , G06F12/02 , G06F16/22 , G06F16/28
CPC分类号: G06F9/547 , G06F8/41 , G06F8/437 , G06F9/30076 , G06F9/44521 , G06F9/44536 , G06F9/4488 , G06F9/4494 , G06F9/4498 , G06F9/451 , G06F9/45516 , G06F9/541 , G06F9/542 , G06F9/548 , G06F12/023 , G06F16/2272 , G06F16/2291 , G06F16/289
摘要: A parametric constant resolves to different values in different contexts, but a single value within a particular context. An anchor constant is a parametric constant that allows for a degree of parametricity for an API point. The context for the anchor constant is provided by a caller to the API point. The anchor constant resolves to an anchor value that records specialization decisions for the API point within the provided context. Specialization decisions may include type restrictions, memory layout, and/or memory size. The anchor value together with an unspecialized type of the API point result in a specialized type of the API point. A class object representing the specialized type is created. The class object may be accessible to the caller, but the full value of the anchor value is not accessible to the caller. The API point is executed based on the specialization decisions embodied in the anchor value.
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公开(公告)号:US20240069967A1
公开(公告)日:2024-02-29
申请号:US18505626
申请日:2023-11-09
发明人: Kaan Tekelioglu
CPC分类号: G06F9/4881 , G05B15/02 , G06F8/433 , G06F9/3838 , G06F9/4494 , G06F9/451 , G06F9/5072 , G06F2209/486
摘要: A pipeline task verification method and system is disclosed, and may use one or more processors. The method may comprise providing a data processing pipeline specification, wherein the data processing pipeline specification defines a plurality of data elements of a data processing pipeline. The method may further comprise identifying from the data processing pipeline specification one or more tasks defining a relationship between a first data element and a second data element. The method may further comprise receiving for a given task one or more data processing elements intended to receive the first data element and to produce the second data element. The method may further comprise verifying that the received one or more data processing elements receive the first data element and produce the second data element according to the defined relationship.
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公开(公告)号:US20230412365A1
公开(公告)日:2023-12-21
申请号:US18241748
申请日:2023-09-01
申请人: Intel Corporation
发明人: Thomas E. Willis , Brad Burres , Amit Kumar
IPC分类号: H04L9/08 , G06F3/06 , G06F9/50 , H04L69/12 , H04L69/32 , G06F16/25 , G06F16/2453 , H04L49/9005 , G11C8/12 , G11C29/02 , H04L41/0896 , G06F30/34 , B25J15/00 , G06F1/18 , G06F1/20 , G06F11/34 , G06F15/78 , H04L41/5025 , H04L67/1008 , H05K7/14 , H05K7/18 , H05K7/20 , H04L67/1001 , G11C29/36 , G11C29/38 , G11C29/44 , G06F16/22 , G06F16/2455 , G06F12/02 , G06F12/14 , G06F13/16 , G06F15/173 , G06F13/40 , G06F13/42 , G06F9/448 , G06F9/28 , G06F15/16 , H04L41/0893 , H04L69/22 , H04L69/321 , H04L41/0213 , H04L41/0668 , H04L41/0677 , H04L45/28 , H04L45/7453 , H04L47/11 , H04L47/125 , H04L49/00 , H04L49/351 , G06F9/4401 , G06F9/445 , G06F12/06 , G06F16/23 , G06F16/248 , G06F16/901 , G06F16/11
CPC分类号: H04L9/0819 , G06F3/0631 , G06F3/067 , G06F3/0659 , G06F3/0604 , G06F9/5044 , H04L69/12 , H04L69/32 , G06F16/25 , G06F16/2453 , G06F9/5088 , H04L49/9005 , G11C8/12 , G11C29/028 , H04L41/0896 , G06F3/0605 , G06F30/34 , B25J15/0014 , G06F1/183 , G06F1/20 , G06F9/505 , G06F11/3442 , G06F15/7807 , G06F15/7867 , H04L41/5025 , H04L67/1008 , H05K7/1489 , H05K7/18 , H05K7/20209 , H05K7/20736 , H04L67/1001 , G11C29/36 , G11C29/38 , G11C29/44 , G06F16/221 , G06F16/2237 , G06F16/24553 , G06F16/2282 , G06F12/023 , G06F12/14 , G06F13/1663 , G06F15/17331 , G06F3/0611 , G06F13/1668 , G06F13/4068 , G06F13/42 , G06F3/0613 , G06F3/0629 , G06F9/4494 , G06F9/28 , G06F15/161 , G06F3/0644 , G06F3/0683 , H04L41/0893 , H04L69/22 , H04L69/321 , H04L41/0213 , H04L41/0668 , H04L41/0677 , H04L45/28 , H04L45/7453 , H04L47/11 , H04L47/125 , H04L49/30 , H04L49/351 , G06F9/4406 , G06F9/4411 , G06F9/445 , G06F3/0632 , G06F3/065 , G06F3/0685 , G06F3/0673 , G06F12/0607 , G06F16/2455 , G06F16/2365 , G06F16/248 , G06F16/2255 , G06F16/9014 , G06F16/119 , G06F3/0647 , G06F12/06 , H04L9/0894 , G06F2209/509 , G06F9/4401 , G06F9/44
摘要: Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.
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公开(公告)号:US20190250941A1
公开(公告)日:2019-08-15
申请号:US16343401
申请日:2017-10-18
申请人: SRC LABS, LLC
CPC分类号: G06F9/45558 , G06F9/4494 , G06F9/5072 , G06F17/5054 , G06F2009/45591 , H04L67/2861
摘要: The FPGA PaaS enables enterprise developers to easily build applications using its' marketplace components, apps, and stream services. The FPGA PaaS provides its capabilities to its FPGA PaaS enterprise developers.
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7.
公开(公告)号:US20190163501A1
公开(公告)日:2019-05-30
申请号:US16256325
申请日:2019-01-24
CPC分类号: G06F9/4494 , G06F9/445 , G06F16/24
摘要: Computer-implemented methods are provided for preparing an application for execution within an application execution environment and for running an application within an application execution environment. The computer-implemented methods create supplementary information for the application. The supplementary information includes an indication of a service request which is to be performed during execution of the application to obtain information from an application service. The computer-implemented methods retrieve the supplementary information for the application, and execute the application within the application execution environment. The methods perform the service request from the application execution environment independently from the execution of the application based on the supplementary information, and receive a response to the service request from the application service at the application execution environment. The method provides the response from the application execution environment to the application in response to a request from the application to perform the service request.
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8.
公开(公告)号:US20190102217A1
公开(公告)日:2019-04-04
申请号:US16143632
申请日:2018-09-27
发明人: Hermann Kopetz
CPC分类号: G06F9/485 , G05B19/0423 , G06F9/4494 , G06F9/4887 , G06F17/11 , H04L12/40026
摘要: A method for a determination of the optimal duration of a time slot for computational actions in a time-triggered controller. The controller includes a sensor subsystem, a computational subsystem, an actuator subsystem, and a time-triggered communication system. The time-triggered communication system is placed between the sensor subsystem, the computational subsystem, the actuator subsystem, and a monitor subsystem. An anytime algorithms is executed in the computational subsystem. A plurality of execution slot durations of the anytime algorithms is probed during the development phase, starting from the minimum execution slot duration, increasing this slot duration by the execution slot granularity until the maximum execution slot duration is reached. In each of the execution slot durations, a multitude of frames is executed in a destined application environment. In each frame the computational subsystem calculates imprecise anticipated values of observable state variables by interrupting execution of the anytime algorithm at the end of the provided execution slot duration, using data received from the sensor subsystems at the beginning of the frame.
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公开(公告)号:US20190065224A1
公开(公告)日:2019-02-28
申请号:US16175925
申请日:2018-10-31
申请人: Google LLC
发明人: Craig D. Chambers , Ashish Raniwala , Frances J. Perry , Stephen R. Adams , Robert R. Henry , Robert Bradshaw , Nathan Weizenbaum
IPC分类号: G06F9/455 , G06F21/62 , G06F8/30 , G06F8/34 , G06F8/41 , G06F9/38 , G06F21/57 , G06F9/48 , G06F9/445 , G06F9/44 , G06F17/30 , G06F9/30 , G06F9/448
CPC分类号: G06F9/45504 , G06F8/314 , G06F8/34 , G06F8/433 , G06F9/30 , G06F9/38 , G06F9/3851 , G06F9/3885 , G06F9/44 , G06F9/445 , G06F9/4494 , G06F9/45533 , G06F9/4843 , G06F16/24532 , G06F16/24547 , G06F21/577 , G06F21/62 , G06F21/6218 , G06F2221/034
摘要: A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.
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公开(公告)号:US20180321920A1
公开(公告)日:2018-11-08
申请号:US16038100
申请日:2018-07-17
申请人: MUREX S.A.S.
发明人: FADY CHAMIEH , ELIAS EDDE
CPC分类号: G06F8/315 , G06F8/30 , G06F8/41 , G06F9/4488 , G06F9/4494 , G06F9/45508
摘要: A method and apparatus for producer graph oriented programming and execution. According to one aspect of the invention, a runtime is provided that interprets producer dependency declarations for methods. The producer dependency declarations identify at run time a set of zero or more producers, where a producer is a runtime instantiatable construct that includes at least an instance and a method associated with that instance. The runtime automatically generates and executes, responsive to receiving a designation of a producer of interest whose method has a producer dependency declaration, a producer graph. The producer graph initially includes the producer of interest and is generated, from the producer of interest to source producers, through instantiation of producers based on the producer dependency declarations of the methods of the producers already in the producer graph. The runtime sequences the execution of the producers in the producer graph as indicated by the producer graph.
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