Creating a dynamic address translation with translation exception qualifiers

    公开(公告)号:US10241910B2

    公开(公告)日:2019-03-26

    申请号:US15645819

    申请日:2017-07-10

    摘要: An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

    Creating a program product or system for executing an instruction for pre-fetching data and releasing cache lines
    3.
    发明授权
    Creating a program product or system for executing an instruction for pre-fetching data and releasing cache lines 有权
    创建用于执行预取数据和释放高速缓存行的指令的程序产品或系统

    公开(公告)号:US09069675B2

    公开(公告)日:2015-06-30

    申请号:US14221869

    申请日:2014-03-21

    IPC分类号: G06F12/08 G06F9/30 G06F9/38

    摘要: Systems and Program Products are created to execute a prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction.

    摘要翻译: 创建系统和程序产品以执行具有M字段的预取数据机器指令,以在指定操作数的地址的数据的高速缓存行上执行功能。 该操作包括将来自存储器的数据的高速缓存行预取到高速缓存或减少对高速缓存中的存储和获取或仅获取高速缓存行的访问所有权或其组合。 操作数的地址是基于寄存器值或指向预取数据机器指令的程序计数器值。

    Tracking multiple conditions in a general purpose register and instruction therefor
    4.
    发明授权
    Tracking multiple conditions in a general purpose register and instruction therefor 有权
    跟踪通用寄存器中的多个条件及其指令

    公开(公告)号:US09256427B2

    公开(公告)日:2016-02-09

    申请号:US13710548

    申请日:2012-12-11

    IPC分类号: G06F9/38 G06F9/30

    摘要: An operate-and-insert instruction of a program, when executed performs an operation based on one or more operands, results of an instruction specified test of the operation performed are stored in an instruction specified location of an instruction specified general register. The instruction specified general register is therefore able to hold results of many operate-and-insert instructions. The program can then use non-branch type instructions to evaluate conditions saved in the register, thus avoiding the performance penalty of branch instructions.

    摘要翻译: 程序的操作和插入指令在执行时执行基于一个或多个操作数的操作,所执行的操作的指令测试结果被存储在指令通用寄存器的指令指定位置。 因此,指定通用寄存器的指令能够保存许多操作和插入指令的结果。 然后,程序可以使用非分支类型的指令来评估寄存器中保存的条件,从而避免分支指令的性能损失。

    Creating a program product or system for executing a perform frame management instruction
    5.
    发明授权
    Creating a program product or system for executing a perform frame management instruction 有权
    创建用于执行执行帧管理指令的程序产品或系统

    公开(公告)号:US09158711B2

    公开(公告)日:2015-10-13

    申请号:US14561703

    申请日:2014-12-05

    摘要: Creating a computer program product or a computer system to execute a frame management instruction which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

    摘要翻译: 创建计算机程序产品或计算机系统以执行标识第一和第二通用寄存器的帧管理指令。 第一通用寄存器包含具有带有访问保护位的密钥字段和块大小指示的帧管理字段。 如果块大小指示指示大块,则从第二通用寄存器获得大数据块的操作数地址。 大块数据具有多个小块,每个小块与具有多个存储密钥访问保护位的对应存储密钥相关联。 如果块大小指示指示大块,则使用密钥字段的访问保护位来设置大块内的每个小块的每个相应的存储密钥的存储密钥访问保护位。

    Creating A Dynamic Address Translation With Translation Exception Qualifier
    6.
    发明申请
    Creating A Dynamic Address Translation With Translation Exception Qualifier 有权
    创建具有翻译异常限定符的动态地址转换

    公开(公告)号:US20140181360A1

    公开(公告)日:2014-06-26

    申请号:US14191516

    申请日:2014-02-27

    IPC分类号: G06F12/10 G06F9/455

    摘要: An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

    摘要翻译: 创建增强的动态地址转换设备产品,使得在一个实施例中,获得要转换的虚拟地址和转换表的层级的转换表的初始起始地址。 虚拟地址的动态地址转换进行。 响应于在动态地址转换期间发生的翻译中断,比特被存储在转换异常限定符(TXQ)字段中,以指示异常是在运行主机程序或主机DAT异常发生时发生的主机DAT异常 同时运行一个客人程序。 TXQ还能够指示异常与从访客页面帧实际地址或访客段帧绝对地址导出的主机虚拟地址相关联。 TXQ还能够指示较大或较小的主机帧大小优于后端客机帧。

    Dynamic address translation with translation table entry format control for identifying format of the translation table entry
    8.
    发明授权
    Dynamic address translation with translation table entry format control for identifying format of the translation table entry 有权
    动态地址转换与翻译表格格式控制,用于识别翻译表格的格式

    公开(公告)号:US09244856B2

    公开(公告)日:2016-01-26

    申请号:US14133796

    申请日:2013-12-19

    IPC分类号: G06F12/00 G06F12/10 G06F13/28

    CPC分类号: G06F12/1009 G06F12/1027

    摘要: An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.

    摘要翻译: 提供增强的动态地址转换工具。 在一个实施例中,获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的索引部分用于引用转换表中的条目。 如果启用了转换表条目中包含的格式控制字段,则表项包含大小至少为1M字节的大块数据的帧地址。 然后将帧地址与虚拟地址的偏移部分组合以形成主存储器或存储器中的小4K字节数据块的转换地址。