公开(公告)号：US10073802B2

公开(公告)日：2018-09-11

申请号：US15250067

申请日：2016-08-29

Applicant: IMEC VZW ,  Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Praveen Raghavan

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F13/4022 ,  G06F13/4282 ,  G06F15/17362 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P

公开(公告)号：US20180101483A1

公开(公告)日：2018-04-12

申请号：US15726749

申请日：2017-10-06

Applicant: IMEC VZW ,  Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Matthias Hartmann ,  Jose Ignacio Gomez ,  Christian Tenllado ,  Sotiris Xydis ,  Javier Setoain Rodrigo ,  Thomas Papastergiou ,  Christos Baloukas ,  Anup Kumar Das ,  Dimitrios Soudris

IPC: G06F12/1045 ,  G06F12/0811 ,  G06F12/122 ,  G06F12/128

CPC classification number: G06F12/1054 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0864 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/122 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/2515 ,  G06F2212/283 ,  G06F2212/502 ,  G06F2212/621 ,  G06F2212/652 ,  Y02D10/13

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

公开(公告)号：US10592430B2

公开(公告)日：2020-03-17

申请号：US15726749

申请日：2017-10-06

Applicant: IMEC VZW ,  Stichting IMEC Nederland ,  UNIVERSIDAD COMPLUTENSE DE MADRID

Inventor： Francky Catthoor ,  Matthias Hartmann ,  Jose Ignacio Gomez ,  Christian Tenllado ,  Sotiris Xydis ,  Javier Setoain Rodrigo ,  Thomas Papastergiou ,  Christos Baloukas ,  Anup Kumar Das ,  Dimitrios Soudris

IPC: G06F12/00 ,  G06F12/1045 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/122 ,  G06F12/128 ,  G06F12/0864 ,  G06F12/08 ,  G06F12/02

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

公开(公告)号：US20170083469A1

公开(公告)日：2017-03-23

申请号：US15250067

申请日：2016-08-29

Applicant: IMEC VZW ,  Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Praveen Raghavan

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4282 ,  G06F15/17362 ,  G06F15/7807

Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P

公开(公告)号：US20220100941A1

公开(公告)日：2022-03-31

申请号：US17449383

申请日：2021-09-29

Applicant: IMEC vzw ,  Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Jan Stuijt ,  Sandeep Pande

IPC: G06F30/343

Abstract: The present disclosure relates to a memory device comprising a memory array and a periphery circuitry configured to read data from and/or write data to the memory array, wherein the periphery circuitry comprises a programmable circuitry causing the memory device to access data stored in the memory array in accordance with manifest loop instructions. The programmable circuitry comprises a control logic configured to control the operation of the periphery circuitry in accordance with a set of parameters derived from the manifest loop instructions. The present disclosure further relates to a method for controlling the operation of a memory device and to a processing system comprising the memory device.

公开(公告)号：US09244701B2

公开(公告)日：2016-01-26

申请号：US13940247

申请日：2013-07-11

Applicant: IMEC ,  Stichting IMEC Nederland ,  Katholieke Universiteit Leuven, K.U. LEUVEN R&D

Inventor： Francky Catthoor ,  Evangelos Bempelis ,  Wim Van Thillo ,  Praveen Raghavan ,  Robert Fasthuber ,  Elena Hammari ,  Per Gunnar Kjeldsberg ,  Jos Huisken

IPC: G06F3/0484 ,  G06F9/445 ,  G06F17/50

CPC classification number: G06F9/44505 ,  G06F17/5045

Abstract: Methods are disclosed for system scenario-based design for an embedded platform whereon a dynamic application is implemented. The application meets at least one guaranteed constraint. Temporal correlations are assumed in the behavior of internal data variables used in the application, with the internal data variables representing parameters used for executing a portion of the application. An example method includes determining a distribution over time of an N-dimensional cost function, with N an integer number N≧1, corresponding to the implementation on the platform for a set of combinations of the internal data variables. The method also includes partitioning an N-dimensional cost space in at least two bounded regions, each bounded region containing cost combinations corresponding to combinations of values of the internal data variables of the set that have similar cost and frequency of occurrence, whereby one bounded region is provided for rarely occurring cost combinations.

Abstract translation: 对于实现动态应用的嵌入式平台，公开了基于系统场景的设计的方法。 应用程序满足至少一个保证约束。 在应用程序中使用的内部数据变量的行为假定时间相关性，内部数据变量表示用于执行应用程序的一部分的参数。 一个示例性方法包括确定N维成本函数的分布，N为整数N≥1，对应于平台上对于内部数据变量的组合的集合的实现。 该方法还包括在至少两个有界区域中分割N维成本空间，每个有界区域包含对应于具有类似成本和发生频率的集合的内部数据变量的值的组合的成本组合，由此一个有界区域 是为很少出现的成本组合提供的。

公开(公告)号：US20140019739A1

公开(公告)日：2014-01-16

申请号：US13940247

申请日：2013-07-11

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. LEUVEN R&D ,  Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Evangelos Bebelis ,  Wim Van Thillo ,  Praveen Raghavan ,  Robert Fasthuber ,  Elena Hammari ,  Per Gunnar Kjeldsberg ,  Jos Huisken

IPC: G06F9/445

CPC classification number: G06F9/44505 ,  G06F17/5045

Abstract: Methods are disclosed for system scenario-based design for an embedded platform whereon a dynamic application is implemented. The application meets at least one guaranteed constraint. Temporal correlations are assumed in the behaviour of internal data variables used in the application, with the internal data variables representing parameters used for executing a portion of the application. An example method includes determining a distribution over time of an N-dimensional cost function, with N an integer number N≧1, corresponding to the implementation on the platform for a set of combinations of the internal data variables. The method also includes partitioning an N-dimensional cost space in at least two bounded regions, each bounded region containing cost combinations corresponding to combinations of values of the internal data variables of the set that have similar cost and frequency of occurrence, whereby one bounded region is provided for rarely occurring cost combinations.

Abstract translation: 对于实现动态应用的嵌入式平台，公开了基于系统场景的设计的方法。 应用程序满足至少一个保证约束。 在应用程序中使用的内部数据变量的行为假定时间相关性，内部数据变量表示用于执行应用程序的一部分的参数。 一个示例性方法包括确定N维成本函数的分布，其中N是整数N≥1，对应于平台上对于内部数据变量的组合的集合的实现。 该方法还包括在至少两个有界区域中分割N维成本空间，每个有界区域包含对应于具有类似成本和发生频率的集合的内部数据变量的值的组合的成本组合，由此一个有界区域 是为很少出现的成本组合提供的。

公开(公告)号：US20140071737A1

公开(公告)日：2014-03-13

申请号：US14015822

申请日：2013-08-30

Applicant: Katholieke Universiteit Leuven ,  Stichting IMEC Nederland

Inventor： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/18 ,  G11C11/412

Abstract: A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.

Abstract translation: 具有互补的全局和局部位线的存储器件，所述互补局部位线可通过本地写入接收器连接到所述互补的全局位线，所述本地写入接收器经配置以在互补的局部位线上产生全电压摆幅， 在互补的全局位线上降低电压摆幅。 本地写接收器包括用于将本地连接到全局位线的连接机构和直接连接到互补局部位线的一对交叉耦合的反相器，用于将互补局部位上的降低的电压摆幅转换为全电压摆幅 线条。

公开(公告)号：US20160179577A1

公开(公告)日：2016-06-23

申请号：US14975142

申请日：2015-12-18

Applicant: Stichting IMEC Nederland

Inventor： Francky Catthoor ,  Dimitrios Rodopoulos ,  Dimitrios Soudris

IPC: G06F9/50

CPC classification number: G06F9/505 ,  G06Q10/04

Abstract: The present disclosure relates to a method of managing the operation of a digital synchronous electronic system with a guaranteed lifetime, using digital processing means. The method comprises: monitoring the electronic system at run time, while the electronic system executes a set of application tasks currently running on the electronic system in a current system working mode; detecting a violation in at least one parameter of the electronic system, the violation affecting one or more guaranteed objectives or one or more cost functions; selecting at least one condition to revise the current system working mode of the electronic system; and based on the at least one condition, selecting a revised system working mode to continue execution of the set of application tasks.

Abstract translation: 本公开涉及使用数字处理装置来管理具有保证寿命的数字同步电子系统的操作的方法。 该方法包括：在电子系统在当前系统工作模式下执行当前在电子系统上运行的一组应用任务的运行时监视电子系统; 检测电子系统的至少一个参数中的违规，影响一个或多个保证目标的违规或一个或多个成本函数; 选择至少一个条件来修改电子系统的当前系统工作模式; 并且基于所述至少一个条件，选择修改的系统工作模式以继续执行所述一组应用任务。

公开(公告)号：US08958238B2

公开(公告)日：2015-02-17

申请号：US14015822

申请日：2013-08-30

Applicant: Stichting IMEC Nederland ,  Katholieke Universiteit Leuven

Inventor： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

IPC: G11C11/419 ,  G11C11/412 ,  G11C7/18

CPC classification number: G11C11/419 ,  G11C7/18 ,  G11C11/412

Abstract: A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.

Abstract translation: 具有互补的全局和局部位线的存储器件，所述互补局部位线可通过本地写入接收器连接到所述互补的全局位线，所述本地写入接收器经配置以在互补的局部位线上产生全电压摆幅， 在互补的全局位线上降低电压摆幅。 本地写接收器包括用于将本地连接到全局位线的连接机构和直接连接到互补局部位线的一对交叉耦合的反相器，用于将互补局部位上的降低的电压摆幅转换为全电压摆幅 线条。