公开(公告)号：US09996499B2

公开(公告)日：2018-06-12

申请号：US13248869

申请日：2011-09-29

Applicant: Dusan Suvakovic ,  Adriaan J. de Lind van Wijngaarden ,  Man Fai Lau

Inventor： Dusan Suvakovic ,  Adriaan J. de Lind van Wijngaarden ,  Man Fai Lau

IPC: G06F15/78 ,  G06F9/38

CPC classification number: G06F15/7867 ,  G06F9/3897 ,  Y02D10/12 ,  Y02D10/13

Abstract: A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.

公开(公告)号：US09842180B2

公开(公告)日：2017-12-12

申请号：US14585864

申请日：2014-12-30

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Ting-Shuo Hsu ,  Jing-Jia Liou ,  Jih-Sheng Shen ,  Juin-Ming Lu

IPC: G06F17/50 ,  G06F15/78 ,  G06F1/32

CPC classification number: G06F17/5045 ,  G06F1/32 ,  G06F15/7825 ,  G06F17/5031 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/84 ,  Y02D10/12 ,  Y02D10/13

Abstract: A NoC timing power estimating method includes: estimating a plurality of transmission timing of a plurality of transmission units of at least a packet, the transmission timing indicating respective time points at which the transmission units enter/leave a plurality of passing elements of the NoC; based on the transmission timing of the transmission units, estimating respective circuit states and respective power states of the passing elements of the NoC, the circuit state indicating an operation state of the passing element and the power state being related to the circuit state; and based on the power states of the passing elements of the NoC, estimating power consumption of the NoC.

公开(公告)号：US09825844B2

公开(公告)日：2017-11-21

申请号：US15365460

申请日：2016-11-30

Applicant: Futurewei Technologies, Inc.

Inventor： Iulin Lih ,  William Lynch

IPC: H04L12/24 ,  H04L12/721 ,  H04L12/437 ,  G06F15/173 ,  G06F15/78 ,  H04L12/42 ,  H04L12/715 ,  H04L12/741

CPC classification number: H04L45/12 ,  G06F15/17362 ,  G06F15/7825 ,  H04L12/42 ,  H04L12/437 ,  H04L45/06 ,  H04L45/64 ,  H04L45/745 ,  H04L2012/421 ,  Y02D10/12 ,  Y02D10/13

Abstract: An interconnection system comprising a plurality of nodes, each comprising at least two ports, and a plurality of links configured to interconnect ports among the nodes to form a hierarchical multi-level ring topology, wherein the ring topology comprises a plurality of levels of rings including a base ring and at least two hierarchical shortcut rings, and wherein each node connected to a higher-level shortcut ring is also connected to all lower-level rings including the base ring.

公开(公告)号：US09792249B2

公开(公告)日：2017-10-17

申请号：US14753948

申请日：2015-06-29

Applicant: III HOLDINGS 2, LLC

Inventor： David Borland ,  Arnold Thomas Schnell ,  Mark Davis

IPC: G06F15/78 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F15/7803 ,  G06F13/4068 ,  G06F13/4282 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system and method for provisioning of modular compute resources within a system design are provided. In one embodiment, a node card or a system board may be used.

公开(公告)号：US09720730B2

公开(公告)日：2017-08-01

申请号：US13995994

申请日：2011-12-30

Applicant: Boris Ginzburg ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Michael Mishaeli ,  Alon Naveh ,  David A. Koufaty ,  Scott D. Hahn ,  Tong Li ,  Avi Mendleson ,  Eugene Gorbatov ,  Hisham Abu-Salah ,  Dheeraj R. Subbareddy ,  Paolo Narvaez ,  Aamer Jaleel ,  Efraim Rotem ,  Yuval Yosef ,  Anil Aggarwal ,  Kenzo Van Craeynest

Inventor： Boris Ginzburg ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Michael Mishaeli ,  Alon Naveh ,  David A. Koufaty ,  Scott D. Hahn ,  Tong Li ,  Avi Mendleson ,  Eugene Gorbatov ,  Hisham Abu-Salah ,  Dheeraj R. Subbareddy ,  Paolo Narvaez ,  Aamer Jaleel ,  Efraim Rotem ,  Yuval Yosef ,  Anil Aggarwal ,  Kenzo Van Craeynest

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F9/30 ,  G06F15/78

CPC classification number: G06F9/4881 ,  G06F9/30101 ,  G06F9/4856 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/24 ,  Y02D10/32

Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

公开(公告)号：US20170153892A1

公开(公告)日：2017-06-01

申请号：US14953529

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Leo A. Linsky

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F15/80

CPC classification number: G06F9/30029 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3897 ,  G06F12/0811 ,  G06F12/0875 ,  G06F15/7807 ,  G06F15/80 ,  G06F2212/452 ,  Y02D10/12 ,  Y02D10/13

Abstract: In one embodiment, a processor includes: a first core to execute instructions; and a programmable fabric having a hierarchical arrangement including a first layer of programmable fabric and a second layer of programmable fabric. The programmable fabric may include a fabric interface controller to: receive a first programmable fabric control instruction from the first core; and responsive thereto, cause a first programmable fabric unit of the first layer of programmable fabric to execute an operation on first input data. Other embodiments are described and claimed.

公开(公告)号：US20170090930A1

公开(公告)日：2017-03-30

申请号：US14863755

申请日：2015-09-24

Applicant: QUALCOMM Incoporated

Inventor： Shivam Priyadarshi ,  Anil Krishna ,  Raguram Damodaran

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3885 ,  G06F11/3024 ,  G06F11/3452 ,  G06F15/7878 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/34

Abstract: Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction is disclosed. In one aspect, a pipeline reconfiguration circuit is communicatively coupled to an execution pipeline providing multiple selectable pipeline configurations. The pipeline reconfiguration circuit generates a phase identifier (ID) for a phase based on a preceding phase. The phase ID is used as an index into an entry of a pipeline configuration prediction (PCP) table to determine whether training for the phase is ongoing. If so, the pipeline reconfiguration circuit performs multiple training cycles, each employing a pipeline configuration from the selectable pipeline configurations for the execution pipeline, to determine a preferred pipeline configuration for the phase. If training for the phase is complete, the pipeline reconfiguration circuit reconfigures the execution pipeline into the preferred pipeline configuration indicated by the entry before the phase is executed.

公开(公告)号：US09608922B2

公开(公告)日：2017-03-28

申请号：US13993575

申请日：2011-12-23

Applicant: Matteo Monchiero ,  Javier Carretero Casado ,  Enric Herrero Abellanas ,  Tanausu Ramirez ,  Xavier Vera

Inventor： Matteo Monchiero ,  Javier Carretero Casado ,  Enric Herrero Abellanas ,  Tanausu Ramirez ,  Xavier Vera

IPC: H04L12/24 ,  H04L12/825 ,  G06F15/78

CPC classification number: H04L47/25 ,  G06F15/7825 ,  H04L47/263 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D50/10

Abstract: An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.

公开(公告)号：US20170085463A1

公开(公告)日：2017-03-23

申请号：US15365460

申请日：2016-11-30

Applicant: Futurewei Technologies, Inc.

Inventor： Iulin Lih ,  William Lynch

IPC: H04L12/721 ,  H04L12/741 ,  H04L12/715 ,  H04L12/42

CPC classification number: H04L45/12 ,  G06F15/17362 ,  G06F15/7825 ,  H04L12/42 ,  H04L12/437 ,  H04L45/06 ,  H04L45/64 ,  H04L45/745 ,  H04L2012/421 ,  Y02D10/12 ,  Y02D10/13

Abstract: An interconnection system comprising a plurality of nodes, each comprising at least two ports, and a plurality of links configured to interconnect ports among the nodes to form a hierarchical multi-level ring topology, wherein the ring topology comprises a plurality of levels of rings including a base ring and at least two hierarchical shortcut rings, and wherein each node connected to a higher-level shortcut ring is also connected to all lower-level rings including the base ring.

公开(公告)号：US09594723B2

公开(公告)日：2017-03-14

申请号：US13799393

申请日：2013-03-13

Applicant: Altera Corporation

Inventor： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC: G06F15/00 ,  G06F15/78

CPC classification number: G06F15/7867 ,  G06F13/40 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.

Abstract translation: 自适应计算引擎（ACE）IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，控制器操作，存储器操作 和位级操作。 优选的系统实施例包括耦合到提供操作模式所需的配置信息的ACE集成电路。 优选的方法包括生成和提供各种操作模式的配置信息的各种手段。