公开(公告)号：US20190041951A1

公开(公告)日：2019-02-07

申请号：US16012623

申请日：2018-06-19

Applicant: Dorit Shapira ,  Anand K. Enamandram ,  Daniel Cartagena ,  Krishnakanth Sistla ,  Jorge P. Rodriguez ,  Efraim Rotem ,  Nir Rosenzweig

Inventor： Dorit Shapira ,  Anand K. Enamandram ,  Daniel Cartagena ,  Krishnakanth Sistla ,  Jorge P. Rodriguez ,  Efraim Rotem ,  Nir Rosenzweig

IPC: G06F1/32

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

公开(公告)号：US20180232330A1

公开(公告)日：2018-08-16

申请号：US15430345

申请日：2017-02-10

Applicant: ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  DORON RAJWAN ,  HISHAM ABU SALAH ,  ARIEL GUR ,  Guy M. THERIEN ,  RUSSELL J. FENGER

Inventor： ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  DORON RAJWAN ,  HISHAM ABU SALAH ,  ARIEL GUR ,  Guy M. THERIEN ,  RUSSELL J. FENGER

IPC: G06F13/24 ,  G06F1/32 ,  G06F9/30

CPC classification number: G06F13/24 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/44 ,  G06F9/4411

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US20180095520A1

公开(公告)日：2018-04-05

申请号：US15281806

申请日：2016-09-30

Applicant: DORON RAJWAN ,  EFRAIM ROTEM ,  AVINASH N. ANANTHAKRISHNAN ,  ANKUSH VARMA ,  ASSAF GANOR ,  NIR ROSENZWEIG ,  DAVID M. PAWLOWSKI ,  ARIK GIHON ,  NADAV SHULMAN

Inventor： DORON RAJWAN ,  EFRAIM ROTEM ,  AVINASH N. ANANTHAKRISHNAN ,  ANKUSH VARMA ,  ASSAF GANOR ,  NIR ROSENZWEIG ,  DAVID M. PAWLOWSKI ,  ARIK GIHON ,  NADAV SHULMAN

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/28 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.

公开(公告)号：US09619009B2

公开(公告)日：2017-04-11

申请号：US12980532

申请日：2010-12-29

Applicant: Efraim Rotem ,  Oren Lamdan ,  Alon Naveh

Inventor： Efraim Rotem ,  Oren Lamdan ,  Alon Naveh

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875

CPC classification number: G06F1/3287 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/30083 ,  G06F9/3814 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at a performance level different than a performance level at which another one of the plurality of processor cores may operate. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. Other embodiments are also disclosed.

公开(公告)号：US09164397B2

公开(公告)日：2015-10-20

申请号：US13188623

申请日：2011-07-22

Applicant: Amnon Manassen ,  Daniel Kandel ,  Moshe Baruch ,  Joel L. Seligson ,  Alexander Svizher ,  Guy Cohen ,  Efraim Rotem ,  Ohad Bachar ,  Daria Negri ,  Noam Sapiens

Inventor： Amnon Manassen ,  Daniel Kandel ,  Moshe Baruch ,  Joel L. Seligson ,  Alexander Svizher ,  Guy Cohen ,  Efraim Rotem ,  Ohad Bachar ,  Daria Negri ,  Noam Sapiens

IPC: G01B9/02 ,  G03F7/20 ,  G01N21/55

CPC classification number: G03F7/70633 ,  G01N21/55 ,  G03F7/70616

Abstract: The present invention includes an illumination source, at least one illumination symmetrization module (ISM) configured to symmetrize at least a portion of light emanating from the illumination source, a first beam splitter configured to direct a first portion of light processed by the ISM along an object path to a surface of one or more specimens and a second portion of light processed by the ISM along a reference path, and a detector disposed along a primary optical axis, wherein the detector is configured to collect a portion of light reflected from the surface of the one or more specimens.

Abstract translation: 本发明包括照明源，至少一个照明对称化模块（ISM），被配置为对来自照明源发出的光的至少一部分进行对称;第一分束器，被配置为将由ISM处理的光的第一部分沿着 一个或多个样本的表面的物体路径和沿着基准路径由ISM处理的光的第二部分以及沿着主光轴布置的检测器，其中检测器被配置为收集从表面反射的光的一部分 的一个或多个标本。

公开(公告)号：US09122464B2

公开(公告)日：2015-09-01

申请号：US13335831

申请日：2011-12-22

Applicant: Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

Inventor： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

IPC: G06F1/00 ,  G06F1/20 ,  G06F1/32

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/16 ,  Y02D10/171

Abstract: Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.

Abstract translation: 本发明的实施例涉及使用零电压处理器状态的电子设备处理器的节能和节省热节流。 例如，处理器管芯可以包括功率控制单元（PCU）和具有电源门和热传感器的执行单元。 PCU连接到热传感器，以确定执行单元的温度是否已经增加到大于上限阈值，例如当执行单元处理处于活动处理器电源状态的数据时。 PCU也连接到电源门，因此在这种检测时，它可以将主处理器的电源状态改变到零处理器电源状态，以降低执行单元的温度。 当传感器检测到温度降低到低于下限阈值时，PCU可以将处理器电源状态改变回活动状态。

公开(公告)号：US09098261B2

公开(公告)日：2015-08-04

申请号：US13326586

申请日：2011-12-15

Applicant: Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有核心的处理器和用于控制处理器的电源管理特征的功率控制器。 功率控制器可以从核心接收能量性能偏差（EPB）值，并根据该值访问功率性能调谐表。 使用表中的信息，可以更新电源管理功能的至少一个设置。 描述和要求保护其他实施例。

公开(公告)号：US09075610B2

公开(公告)日：2015-07-07

申请号：US13327692

申请日：2011-12-15

Applicant: Eliezer Weissmann ,  Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Alon Naveh ,  Hisham Abu Salah ,  Nadav Shulman

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Alon Naveh ,  Hisham Abu Salah ,  Nadav Shulman

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3234 ,  Y02D10/152 ,  Y02D50/20

Abstract: An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment.

Abstract translation: 这里描述了用于线程合并的装置，方法和系统。 当前的处理器利用率得到确定。 并且从处理器利用率和其他执行参数来识别合并机会，例如在合并之后估计新的利用率，确定基于新利用率是否能够节省能源，以及执行线程迁移/合并到活动处理元件的子集。 一旦执行整合，现在处于空闲状态的非子集处理元件被关闭以节省能量并提供节能的执行环境。

公开(公告)号：US20150091550A1

公开(公告)日：2015-04-02

申请号：US14040346

申请日：2013-09-27

Applicant: EFRAIM ROTEM ,  NIR ROSENZWEIG ,  JEFFREY A. CARLSON ,  PHILIP R. LEHWALDER ,  NADAV SHULMAN ,  DORON RAJWAN

Inventor： EFRAIM ROTEM ,  NIR ROSENZWEIG ,  JEFFREY A. CARLSON ,  PHILIP R. LEHWALDER ,  NADAV SHULMAN ,  DORON RAJWAN

IPC: G01R19/252

CPC classification number: G01R31/3648 ,  G01R21/133 ,  G01R22/10 ,  G01R31/3624

Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

Abstract translation: 公开了用于耦合到诸如移动计算设备或无线电话中的IC的电池供电单元的集成电路（IC）设备的实例，以在快速动态的情况下精确地确定从电源单元获取的能量使用。 来自电源单元的电力线的电流感测信号被数字化。 数字化电流检测以与来自电源单元的电力线的电压近似成比例的速率被添加到累加器。 然后将累加器输出并缩放到与能量测量相关的单位。 能量测量用于估计剩余电池寿命。 触发电流检测信号的数字化可以通过使用脉冲发生电路，或者通过使用累加器的溢出指示符来进行数字化的电压检测信号。 其他的例子被描述和要求保护。

公开(公告)号：US20150006971A1

公开(公告)日：2015-01-01

申请号：US13931115

申请日：2013-06-28

Applicant: Dorit Shapira ,  Krishnakanth V. Sistla ,  Efraim Rotem ,  Nadav Shulman ,  Shmulik Zobel ,  Allen Chu

Inventor： Dorit Shapira ,  Krishnakanth V. Sistla ,  Efraim Rotem ,  Nadav Shulman ,  Shmulik Zobel ,  Allen Chu

IPC: G06F11/30 ,  G06F1/28

CPC classification number: G06F11/3024 ,  G06F11/004 ,  G06F11/008 ,  G06F11/3058

Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.

Abstract translation: 用于跟踪处理器上的应力并响应于控制操作条件的装置和方法。 例如，处理器的一个实施例包括：应力跟踪逻辑，用于基于处理器的一个或多个部分的当前操作条件来确定处理器的一个或多个部分所经受的应力; 以及压力控制逻辑，以基于所确定的应力和目标应力累积速率来控制处理器的一个或多个操作特性。