公开(公告)号：US20190004582A1

公开(公告)日：2019-01-03

申请号：US15635307

申请日：2017-06-28

申请人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3296

摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US20170371401A1

公开(公告)日：2017-12-28

申请号：US15190417

申请日：2016-06-23

申请人： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

发明人： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

IPC分类号： G06F1/32 ,  G06F9/30

CPC分类号： G06F1/3296 ,  G06F1/3228 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3851

摘要： In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

公开(公告)号：US20170153984A1

公开(公告)日：2017-06-01

申请号：US15394458

申请日：2016-12-29

申请人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

发明人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

IPC分类号： G06F12/1027 ,  G06F12/1009

CPC分类号： G06F9/3851 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US09652018B2

公开(公告)日：2017-05-16

申请号：US13997200

申请日：2011-12-30

申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/3203

摘要： Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170109281A1

公开(公告)日：2017-04-20

申请号：US15394539

申请日：2016-12-29

申请人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

发明人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

IPC分类号： G06F12/0811 ,  G06F12/1009 ,  G06F12/1027

CPC分类号： G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US09600058B2

公开(公告)日：2017-03-21

申请号：US14313597

申请日：2014-06-24

申请人： Hisham Abu Salah ,  Eliezer Weissmann ,  Efraim Rotem ,  Paul S. Diefenbaugh ,  Jay D. Schwartz ,  Sharad C. Tripathi

发明人： Hisham Abu Salah ,  Eliezer Weissmann ,  Efraim Rotem ,  Paul S. Diefenbaugh ,  Jay D. Schwartz ,  Sharad C. Tripathi

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3206 ,  G06F1/3293 ,  Y02D10/126

摘要： Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

公开(公告)号：US09396020B2

公开(公告)日：2016-07-19

申请号：US13993273

申请日：2012-03-30

申请人： Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann ,  Karthikeyan Vaithianathan ,  Ehud Cohen

发明人： Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann ,  Karthikeyan Vaithianathan ,  Ehud Cohen

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/461 ,  G06F9/485

摘要： An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator.

摘要翻译： 描述了具有多个芯的装置，每个芯具有：a）加速器; 和b）耦合到加速器的通用CPU。 通用CPU具有功能单元逻辑电路，以执行返回一定量的存储空间以存储加速器的上下文信息的指令。

公开(公告)号：US09361101B2

公开(公告)日：2016-06-07

申请号：US13538252

申请日：2012-06-29

申请人： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/461

摘要： A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

摘要翻译： 处理器可以节省微架构上下文以提高代码执行和电源管理的效率。 执行保存指令以在停止进程的执行的上下文切换时将微架构状态和处理器的体系结构状态存储在存储器的公共缓冲器中。 微架构状态包含执行该过程所产生的性能数据。 执行恢复指令以在恢复执行该过程时从公共缓冲器检索微架构状态和架构状态。 电源管理硬件然后使用微架构状态作为恢复执行的中间起点。

公开(公告)号：US20150355705A1

公开(公告)日：2015-12-10

申请号：US14298171

申请日：2014-06-06

申请人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

发明人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心和功率控制器。 功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。 此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。 描述和要求保护其他实施例。

公开(公告)号：US09152205B2

公开(公告)日：2015-10-06

申请号：US13596915

申请日：2012-08-28

申请人： Ohad Falik ,  Eliezer Weissmann ,  Alon Naveh ,  Michael Mishaeli ,  Nadav Shulman ,  Robert E. Gough ,  Erik C. Bjorge ,  Douglas R. Moran ,  Peter A. Dice

发明人： Ohad Falik ,  Eliezer Weissmann ,  Alon Naveh ,  Michael Mishaeli ,  Nadav Shulman ,  Robert E. Gough ,  Erik C. Bjorge ,  Douglas R. Moran ,  Peter A. Dice

IPC分类号： G06F1/32 ,  G06F9/44

CPC分类号： G06F1/3206 ,  G06F9/4418

摘要： A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.

摘要翻译： 描述了根据本发明的一个实施例的用于促进计算系统中更快的挂起/恢复操作的机制。 本发明的实施例的方法包括：响应于在计算系统处的睡眠呼叫，将入口处理发起到第一睡眠状态，从第一休眠状态转换到第二休眠状态。 转换可以包括在与计算系统处理器的一个或多个处理器核心相关联的本地存储器处保留处理器上下文的至少一部分。 该方法还可以包括进入第二睡眠状态。