摘要:
An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.
摘要:
In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.
摘要:
A processing device implementing performance scalability prediction is disclosed. A processing device of the disclosure includes a first counter to increment with each cycle of the processing device in which threads of the processing device are active. The processing device further includes a second counter to increment with each cycle of the processing device in which execution units of the processing device are stalled for one of the threads, and an access request from the one of the threads to memory external to the processing device is pending.
摘要:
Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.
摘要:
Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor and one or more components coupled to the processor are modified based on a total platform power consumption value. The platform, in turn, includes the processor and the one or more components. Other embodiments are also disclosed and claimed.
摘要:
A method used in a receiver includes measuring first Received Signal Strength Indications (RSSIs) in respective first communication channels, which are located in a given frequency band and which each have a first channel bandwidth. Based on the first RSSIs, second RSSIs are computed for respective second communication channels, which are located in the given frequency band and which each have a second channel bandwidth that is larger than the first channel bandwidth. At least one of the first and second communication channels over which to receive signals at the receiver are selected using the first and second RSSIs.
摘要:
A method used in a receiver includes measuring first Received Signal Strength Indications (RSSIs) in respective first communication channels, which are located in a given frequency band and which each have a first channel bandwidth. Based on the first RSSIs, second RSSIs are computed for respective second communication channels, which are located in the given frequency band and which each have a second channel bandwidth that is larger than the first channel bandwidth. At least one of the first and second communication channels over which to receive signals at the receiver are selected using the first and second RSSIs.
摘要:
In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.
摘要:
In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.
摘要:
In an embodiment, a processor includes at least one core. The at least one core includes an execution unit and a current protection (IccP) controller. The IccP controller may receive instruction width information associated with one or more instructions of an instruction queue prior to execution of the instructions by the execution unit. The IccP controller may determine an anticipated highest current level (Icc) for the at least one core based on the instruction width information. The IccP controller may generate a request for a first license for the at least one core that is associated with the Icc. Other embodiments are described and claimed.