公开(公告)号：US09990287B2

公开(公告)日：2018-06-05

申请号：US13994122

申请日：2011-12-21

申请人： Shlomo Raikin ,  Raanan Sade ,  Robert Valentine ,  Julius Yuli Mandelblat ,  Ron Shalev ,  Larisa Novakovsky

发明人： Shlomo Raikin ,  Raanan Sade ,  Robert Valentine ,  Julius Yuli Mandelblat ,  Ron Shalev ,  Larisa Novakovsky

IPC分类号： G06F13/38 ,  G06T1/20 ,  G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F13/16 ,  G06T1/60 ,  G09G5/00 ,  G06F12/0866

CPC分类号： G06F12/0811 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3881 ,  G06F12/0866 ,  G06F13/1673 ,  G06F13/38 ,  G06T1/20 ,  G06T1/60 ,  G09G5/006

摘要： An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

公开(公告)号：US09405545B2

公开(公告)日：2016-08-02

申请号：US13993508

申请日：2011-12-30

申请人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

发明人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

IPC分类号： G06F12/08 ,  G06F9/38

CPC分类号： G06F9/3814 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0808 ,  G06F12/0862 ,  G06F2212/6028 ,  G06F2212/62

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

摘要翻译： 根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。 这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

公开(公告)号：US20140380338A1

公开(公告)日：2014-12-25

申请号：US13926089

申请日：2013-06-25

申请人： LEV MAKOVSKY ,  ZEEV SPERBER ,  EFRAIM ROTEM ,  NIR ROSENZWEIG ,  STANISLAV SHWARTSMAN ,  RAANAN SADE ,  IGOR YANOVER ,  GAVRI BERGER ,  TOMER WEINER ,  RON GABOR

发明人： LEV MAKOVSKY ,  ZEEV SPERBER ,  EFRAIM ROTEM ,  NIR ROSENZWEIG ,  STANISLAV SHWARTSMAN ,  RAANAN SADE ,  IGOR YANOVER ,  GAVRI BERGER ,  TOMER WEINER ,  RON GABOR

IPC分类号： G06F9/54

CPC分类号： G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

摘要： In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

公开(公告)号：US20140192069A1

公开(公告)日：2014-07-10

申请号：US13994122

申请日：2011-12-21

申请人： Shlomo Raikin ,  Raanan Sade ,  Robert Valentine ,  Julius Yuli Mandelblat ,  Ron Shalev ,  Larisa Novakovsky

发明人： Shlomo Raikin ,  Raanan Sade ,  Robert Valentine ,  Julius Yuli Mandelblat ,  Ron Shalev ,  Larisa Novakovsky

IPC分类号： G06F13/38 ,  G06F13/16 ,  G06T1/60 ,  G06F12/08 ,  G06T1/20

CPC分类号： G06F12/0811 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3881 ,  G06F12/0866 ,  G06F13/1673 ,  G06F13/38 ,  G06T1/20 ,  G06T1/60 ,  G09G5/006

摘要： An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

摘要翻译： 描述了一种有效地将数据从中央处理单元（CPU）的核心传输到图形处理单元（GPU）的装置和方法。 例如，一种方法的一个实施例包括：将数据写入CPU的核心内的缓冲器，直到指定的数据量被写入为止; 在检测到指定量的数据已被写入时，响应地产生驱逐周期，驱逐循环使数据从缓冲器传送到可由核心和GPU访问的高速缓存; 设置指示以向GPU指示数据在高速缓存中可用; 并且在GPU检测到指示时，在从GPU接收到读取信号时，从高速缓存提供数据给GPU。

公开(公告)号：US08352683B2

公开(公告)日：2013-01-08

申请号：US12823047

申请日：2010-06-24

申请人： Ehud Cohen ,  Oleg Margulis ,  Raanan Sade ,  Stanislav Shwartsman

发明人： Ehud Cohen ,  Oleg Margulis ,  Raanan Sade ,  Stanislav Shwartsman

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F1/00

CPC分类号： G06F12/0864 ,  G06F12/0859 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

摘要： A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.

摘要翻译： 一种降低存储器件功耗的方法和系统。 在本发明的一个实施例中，存储器件是N路组合关联级（L1）高速缓冲存储器，并且存在与数据高速缓冲存储器耦合的逻辑，以便于仅访问N- 响应于加载指令或存储指令，单向设置关联L1高速缓冲存储器。 通过减少针对每个加载或存储请求访问N路组合关联的L1高速缓冲存储器的方法的数量，在本发明的一个实施例中，减少了N路组合关联的L1高速缓冲存储器的功率需求。 在本发明的一个实施例中，当预测到对高速缓存存储器的访问仅需要N路组关联的L1高速缓冲存储器的数据阵列时，对填充缓冲器的访问被去激活或禁用。

公开(公告)号：US20180095759A1

公开(公告)日：2018-04-05

申请号：US15282011

申请日：2016-09-30

申请人： Raanan Sade ,  Roman Dementiev ,  Ravi Rajwar ,  Ady Tal ,  Alex Gerber

发明人： Raanan Sade ,  Roman Dementiev ,  Ravi Rajwar ,  Ady Tal ,  Alex Gerber

IPC分类号： G06F9/30 ,  G06F12/0855 ,  G06F12/123 ,  G06F12/0875

CPC分类号： G06F9/30043 ,  G06F9/3838 ,  G06F9/466 ,  G06F9/467 ,  G06F12/0857 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/6022

摘要： Suspendable load address tracking inside transactions is disclosed. An example processing device of implementations of the disclosure includes a transactional memory (TM) read set tracking component circuitry to identify a suspend read tracking instruction within a transaction executed by the processing device, mark load instructions occurring in the transaction subsequent to the identified suspend read tracking instruction with a suspend attribute, wherein the addresses corresponding to the marked load instructions are excluded from a read set maintained for the transaction, identify a resume read tracking instruction within the transaction, and stop marking the load instructions occurring subsequent to the identified resume read tracking instruction with the suspend attribute.

公开(公告)号：US20140223105A1

公开(公告)日：2014-08-07

申请号：US13993508

申请日：2011-12-30

申请人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

发明人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3814 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0808 ,  G06F12/0862 ,  G06F2212/6028 ,  G06F2212/62

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

摘要翻译： 根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。 这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

公开(公告)号：US20120072984A1

公开(公告)日：2012-03-22

申请号：US12887898

申请日：2010-09-22

申请人： MICHAEL S. BAIR ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

发明人： MICHAEL S. BAIR ,  David W. Burns ,  Robert S. Chappell ,  Prakash Math ,  Leslie A. Ong ,  Pankaj Raghuvanshi ,  Shlomo Raikin ,  Raanan Sade ,  Michael D. Tucknott ,  Igor Yanover

IPC分类号： G06F21/00

CPC分类号： G06F9/526

摘要： In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，其将定时器与第一线程相关联，并且在完成第一线程之后防止第一线程执行存储器簇操作 原子记忆操作，直到预防窗口过去。 在一些实施例中，该方法可以通过与处理器的存储器执行单元相关联的调节逻辑执行。 描述和要求保护其他实施例。

公开(公告)号：US20100169581A1

公开(公告)日：2010-07-01

申请号：US12346543

申请日：2008-12-30

申请人： Gad Sheaffer ,  Shlomo Raikin ,  Vadim Bassin ,  Raanan Sade ,  Ehud Cohen ,  Oleg Margulis

发明人： Gad Sheaffer ,  Shlomo Raikin ,  Vadim Bassin ,  Raanan Sade ,  Ehud Cohen ,  Oleg Margulis

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F9/3834 ,  G06F9/467 ,  G06F12/0831 ,  G06F12/084

摘要： A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.

摘要翻译： 这里描述了用于扩展高速缓存一致性以保存缓冲数据以支持事务执行的方法和装置。 以缓冲的方式执行引用与数据项相关联的地址的事务存储操作。 这里，与保存数据项的高速缓存行相关联的一致性状态被转换到缓冲状态。 响应缓冲数据项的本地请求，提供数据项以确保内部事务顺序排序。 然而，响应于外部访问请求，提供了错误响应以确保事务更新的数据项在提交之前不会被全局可见。 一旦提交，缓存的行将转换到修改状态，使数据项全局可见。

公开(公告)号：US20220012592A1

公开(公告)日：2022-01-13

申请号：US17483693

申请日：2021-09-23

申请人： Nilesh Jain ,  Menachem Adelman ,  Raanan Sade ,  Ravishankar Iyer ,  Rajesh Poornachandran ,  Yash Akhauri

发明人： Nilesh Jain ,  Menachem Adelman ,  Raanan Sade ,  Ravishankar Iyer ,  Rajesh Poornachandran ,  Yash Akhauri

IPC分类号： G06N3/08 ,  H03M7/30 ,  G06F17/16

摘要： Methods, apparatus, systems, and articles of manufacture to perform weight and activation compression and decompression are disclosed. An example apparatus includes memory, instructions in the apparatus, and processor circuitry to execute the instructions to execute a compression operation to obtain compressed data corresponding to weights in a weight matrix, and determine meta-data associated with the weight matrix, a first portion of the meta-data indicative of whether the weight matrix is compressed, a second portion of the meta-data indicative of a cache size of the compressed data, and a third portion of the meta-data indicative of the compression operation executed to obtain the compressed data.