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1883 条记录 (耗时 0.02 秒)

    CFET CELL ARCHITECTURE WITH A SIDE-ROUTING STRUCTURE
    3.
    发明公开
    CFET CELL ARCHITECTURE WITH A SIDE-ROUTING STRUCTURE 审中-公开

    公开(公告)号：US20240266349A1

    公开(公告)日：2024-08-08

    申请号：US18433779

    申请日：2024-02-06

    申请人： IMEC VZW

    发明人： Gioele Mirabelli ,  Juergen Boemmels ,  Julien Ryckaert

    IPC分类号： H01L27/092 ,  H01L23/528 ,  H01L27/06 ,  H10B10/00

    CPC分类号： H01L27/092 ,  H01L23/5286 ,  H01L27/0688 ,  H10B10/12

    摘要： This disclosure relates to complementary field effect transistor (CFET) devices, and provides improved routability of the transistor structures in a CFET cell. The disclosure presents a CFET cell that includes a first transistor structure in a first tier and a second transistor structure in a second tier above the first tier. A first power rail is arranged below the first tier and connected to the first transistor structure from below, and a second power rail is formed in a first metal layer and connected to the second transistor structure from a first side. A set of signal routing lines formed in a second metal layer above the second tier is connected to the first and second transistor structure from above. Further, a signal routing structure formed in a metal zero (M0) layer is connected to the first transistor structure and/or to the second transistor structure from a second side.

    Method for radar detection and digitally modulated radar robust to IQ imbalance
    6.
    发明授权
    Method for radar detection and digitally modulated radar robust to IQ imbalance 有权

    公开(公告)号：US12025729B2

    公开(公告)日：2024-07-02

    申请号：US17527796

    申请日：2021-11-16

    申请人： Imec vzw

    发明人： Marc Bauduin ,  Andre Bourdoux

    IPC分类号： G01S7/35 ,  G01S13/32 ,  G01S13/58

    CPC分类号： G01S7/354 ,  G01S7/358 ,  G01S13/325 ,  G01S13/58

    摘要： A method is provided for facilitating radar detection robust to IQ imbalance. The method comprises the step of generating a radar signal in digital domain comprising a number of M periodic repetitions of a code sequence with a length Lc, multiplied with a progressive phase rotation





    e

    j
    ·

    π
    K

    ·
    n


    ,




    where Lc and M are integers, K is an integer or a non-integer, and n is a discrete integer variable. The method further comprises the step of generating a process input signal in digital domain from a reflection signal corresponding to the radar signal by multiplying the reflection signal with a progressive phase rotation






    e


    -
    j

    ·

    π
    K

    ·
    n


    .




    In this context, K is defined such that a ratio





    Lc
    K




    is a non-integer, and M is defined such that a ratio






    Lc
    ·
    M

    K




    is an integer.

    Tunneling Enabled Feedback FET
    7.
    发明公开
    Tunneling Enabled Feedback FET 审中-公开

    公开(公告)号：US20240213321A1

    公开(公告)日：2024-06-27

    申请号：US18545730

    申请日：2023-12-19

    申请人： IMEC VZW

    发明人： Aryan Afzalian

    IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/43

    CPC分类号： H01L29/0895 ,  H01L29/0665 ,  H01L29/1033 ,  H01L29/1606 ,  H01L29/432

    摘要： Example embodiments relate to tunneling enabled feedback field effect transistors (FETs). One example system includes a feedback field effect transistor. The feedback field effect transistor includes a source region. The feedback field effect transistor also includes a channel region. Additionally, the feedback field effect transistor includes a drain region. Further, the feedback field effect transistor includes a gate. The channel region is between the source region and the drain region. The source region, the channel region, and the drain region include a semiconductor material with a bandgap that is smaller than 0.9 eV. The source region or the drain region has a dopant concentration that is smaller than 5×1019 cm−3. The gate is positioned along the channel and isolated from the channel.

    SENSING DEVICE AND A METHOD FOR DETECTION OF A CHARACTERISTIC OF A SUBSTANCE AT MULTIPLE TIME POINTS
    8.
    发明公开
    SENSING DEVICE AND A METHOD FOR DETECTION OF A CHARACTERISTIC OF A SUBSTANCE AT MULTIPLE TIME POINTS 审中-公开

    公开(公告)号：US20240210388A1

    公开(公告)日：2024-06-27

    申请号：US18392118

    申请日：2023-12-21

    申请人： IMEC VZW

    发明人： Liesbet LAGAE ,  Olivier HENRY ,  Nick VAN HELLEPUTTE

    IPC分类号： G01N33/543

    CPC分类号： G01N33/5438 ,  G01N33/54306

    摘要： According to an aspect there is provided a sensing device for detection of at least one characteristic of a substance. The sensing device comprises:



    a plurality of cavities, each comprising an opening;
    a plurality of sensors for detecting the at least one characteristic, the plurality of sensors being arranged into a plurality of sets of sensors, each set being arranged in a mutually unique cavity;
    a plurality of protective membranes, each being arranged to cover the opening of the mutually unique cavity, preventing the substance from entering the cavity, thereby protecting the set of sensors from being exposed to the substance.




    The sensing device is configured for providing a different activation timing for different protective membranes, whereby different sets of sensors are exposed to the substance at different points in time, for providing detection of the at least one characteristic at multiple time points.

    Stacked SRAM Cell with a Dual-Side Interconnect Structure
    10.
    发明公开
    Stacked SRAM Cell with a Dual-Side Interconnect Structure 审中-公开

    公开(公告)号：US20240206145A1

    公开(公告)日：2024-06-20

    申请号：US18545760

    申请日：2023-12-19

    申请人： IMEC VZW ,  Katholieke Universiteit Leuven

    发明人： Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin ,  Boon Teik Chan ,  Sujith Subramanian

    IPC分类号： H10B10/00 ,  H01L23/528

    CPC分类号： H10B10/125 ,  H01L23/5286

    摘要： The present disclosure relates to static random access memory (SRAM). In particular, the disclosure provides a stacked SRAM cell, and a method for fabricating the stacked SRAM cell. The stacked SRAM cell comprises two first transistor structures and two second transistor structures, which form a pair of cross-coupled inverters, an comprises one or two pass gate (PG) transistor structures. Further, the stacked SRAM cell comprises a first power rail and/or a second power rail arranged above the transistor structures, wherein the first power rail is connected by respective first vias to the first transistor structures from above, and/or the second power rail is connected by respective second vias to the second transistor structures from above. The SRAM cell also comprises one or two bit lines arranged below the PG transistor structures. Each bit line is connected by a respective third via to one PG transistor structure from below.