公开(公告)号：US11340791B2

公开(公告)日：2022-05-24

申请号：US16742063

申请日：2020-01-14

申请人： Arm Limited

发明人： David Madsen ,  Richard F Bryant

IPC分类号： G06F3/06

摘要： Apparatus comprises source circuitry to provide data items; buffer circuitry having a set of buffer entries to hold one or more data items, provided by the source circuitry, for delivery to one or more destinations within a respective delivery latency, in which a buffer entry holding an initial data item becomes available to hold another data item in response to delivery of the initial data item to its respective destination; and control circuitry to control acceptance of data items from the source circuitry for holding by the buffer circuitry, the control circuitry being configured to control the buffer circuitry to accept a given data item when: (i) a buffer entry is available to hold the given data item and (ii) the delivery latency of data items including the given data item held by the buffer circuitry is such that at least a threshold number of buffer entries may be made available within no more than a threshold availability period.

公开(公告)号：US10901865B2

公开(公告)日：2021-01-26

申请号：US16374103

申请日：2019-04-03

申请人： Arm Limited

发明人： Richard F Bryant ,  Sridharan Balasubramanian ,  Joseph Anthony Delgross

IPC分类号： G06F11/20 ,  G06F11/16

摘要： An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.

公开(公告)号：US10083126B2

公开(公告)日：2018-09-25

申请号：US15370570

申请日：2016-12-06

申请人： ARM Limited

发明人： Richard F Bryant ,  Max John Batley ,  Lilian Atieno Hutchins ,  Sujat Jamil

IPC分类号： G06F12/12 ,  G06F12/10 ,  G06F12/1036

CPC分类号： G06F12/12 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/652 ,  G06F2212/681 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data. A record of the candidate entries in then maintained, and, once the portion of the new data required for conflict detection is available, the conflict detection circuitry then performs a final stage detection operation to determine whether any of the candidate entries do contain data that conflicts with the new data. Any entries identified by the final stage detection operation as containing data that conflicts with the new data are then invalidated. This provides a particularly efficient mechanism for avoiding conflicting entries in a storage structure.