Invention Grant
- Patent Title: Reduction of single event upsets within a semiconductor integrated circuit
- Patent Title (中): 降低半导体集成电路中的单个事件发生
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Application No.: US13666159Application Date: 2012-11-01
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Publication No.: US09000529B1Publication Date: 2015-04-07
- Inventor: Praful Jain , James Karp , Michael J. Hart , Ramakrishna K. Tanikella
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent Kevin T. Cuenot
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L29/06
Abstract:
A circuit includes a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate and an n-well implemented within the p-type substrate that is independent of the storage element. The n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well.
Information query
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