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公开(公告)号：US12235950B2
公开(公告)日：2025-02-25
申请号：US17578292
申请日：2022-01-18
Applicant: XILINX, INC.
Inventor： Jaideep Dastidar , James Murray , Stefano Stabellini
Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.
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公开(公告)号：US12235671B2
公开(公告)日：2025-02-25
申请号：US18199838
申请日：2023-05-19
Applicant: XILINX, INC.
Inventor： Brian C. Gaide
Abstract: An integrated circuit (IC) device includes a circuit comprising pipeline stages, and a controller circuitry configured to: load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of the cycles of the clock signal is based on a quantity of the pipeline stages.
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公开(公告)号：US12231532B1
公开(公告)日：2025-02-18
申请号：US16831356
申请日：2020-03-26
Applicant: XILINX, INC.
Inventor： Devanjan Maiti , Robert Bellarmin Susai , Jayaram Pvss
Abstract: Examples herein describe a scalable tweak engine and prefetching tweak values. Regarding the scalable tweak engine, it can be designed to accommodate different bus widths of data. The scalable tweak engine described herein includes multiple tweak calculators that can be daisy chained together to output multiple tweak values every clock cycle. These tweak values can be sent to multiple encryption cores so that multiple data blocks can be encrypted in parallel. Regarding prefetching tweak values, previous encryption engines incur a delay as the tweak value (e.g., a metadata value) for a data block is calculated. In the embodiments herein, the encryption engine can include an independent metadata engine that determines the metadata value for a subsequent data block while the current data block is being encrypted.
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公开(公告)号：US12224954B2
公开(公告)日：2025-02-11
申请号：US17515343
申请日：2021-10-29
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , Dmitri Kitariev , Derek Roberts
Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.
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5.发明申请公开(公告)号：US20250036848A1
公开(公告)日：2025-01-30
申请号：US18227225
申请日：2023-07-27
Applicant: XILINX, INC.
Inventor： Aashish TRIPATHI , Sundeep Ram Gopal AGARWAL , Ashit DEBNATH , Atreyee SAHA , Praful JAIN
IPC: G06F30/398 , G06F30/392
Abstract: A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each of the windows based on the divided spatial power distribution map and the divided spatial power source node location map, and combining the voltage drop map in each of the windows to form a composite voltage drop map.
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Patent Agency Ranking
公开(公告)号：US12212337B2
公开(公告)日：2025-01-28
申请号：US18128943
申请日：2023-03-30
Applicant: XILINX, INC. , Advanced Micro Devices, Inc.
Inventor： Kumar Rahul , John J. Wuu , Santosh Yachareni
Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.
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公开(公告)号：US20250030500A1
公开(公告)日：2025-01-23
申请号：US18223517
申请日：2023-07-18
Applicant: XILINX, INC.
Inventor： Millind MITTAL , Krishnan SRINIVASAN , Kenneth MA
IPC: H04L1/00 , H04L49/9005
Abstract: Some examples described herein provide for interconnect in chiplet systems, for example system-level techniques for error correction in chip-to-chip interfaces. In an example, a method of error correction includes receiving, at a first chiplet, a data message via a set of interconnect, and transmitting a first control message that requests retransmission of the data message based on detecting an error associated with receiving the data message. The method also includes transmitting one or more instances of a second control message that indicates an idle operation at the first chiplet until the first chiplet receives a third control message that triggers an end of a retransmission mode. The method also includes transmitting a fourth control message frame indicating the end of the retransmission mode, and receiving a retransmission of the data message from the second chiplet.
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公开(公告)号：US12198294B2
公开(公告)日：2025-01-14
申请号：US17591425
申请日：2022-02-02
Applicant: Xilinx, Inc.
Inventor： Karsten Trott
IPC: G06T3/4015 , G06T3/4038 , H04N23/617 , H04N23/84 , H04N23/88
Abstract: A rearranger circuit rearranges data elements of each raw image of a plurality of raw images according to a plurality of raw color channel arrays. The data elements of each raw image are input to the rearranger circuit according to instances of a pattern of color channels of a color filter array (CFA). The data elements specify values of the color channels in the instances of the pattern, and each raw color channel array has the data elements of one color channel of the color channels in the instances of the pattern. The rearranger circuit can be used in neural network training or in generating raw color channel arrays for performing neural network inference.
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公开(公告)号：US20250005249A1
公开(公告)日：2025-01-02
申请号：US18344766
申请日：2023-06-29
Applicant: Xilinx, Inc.
Inventor： Fan Zhang , Chaithanya Dudha , Nithin Kumar Guggilla
IPC: G06F30/392
Abstract: Reducing power consumption of a circuit design includes, for a circuit block of a circuit design, where the circuit block has a plurality of signals, selecting one or more signals of the plurality of signals. Prediction and gating circuitry are generated. The prediction and gating circuitry include a predictor circuit configured to generate a prediction of an output of the circuit block based on the one or more signals as selected and gate the circuit block based on the prediction of the output of the circuit block. The prediction and gating circuitry include an output circuit configured to substitute a constant value as the output of the circuit block responsive to gating the circuit block by the predictor circuit. The prediction and gating circuitry are inserted within the circuit design.
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10.发明申请公开(公告)号：US20250005246A1
公开(公告)日：2025-01-02
申请号：US18345393
申请日：2023-06-30
Applicant: Xilinx, Inc.
Inventor： Chia-Jui Hsu , Fnu Sindhoori
IPC: G06F30/337 , G06F16/22
Abstract: Compiling a tensor specification for multi-dimensional direct memory access circuit configurations includes generating a first list of tile combination objects from a tensor tiling specification. The first list specifies a sequence of tiles specified by the tensor tiling specification in which each tile object represents a single tile of a tensor data structure. A second list of tile combination objects is generated by combining selected ones of the tile combination objects from the first list. Each tile combination object of the second list represents one or more tile objects. The tile combination objects of the second list are converted into buffer descriptor objects that include buffer descriptor parameters. Each of the buffer descriptor objects that is non-compliant with hardware constraints corresponding to a data mover circuit that is configurable using the buffer descriptor objects is legalized. The buffer descriptor objects are output, as legalized.
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