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    SYNCHRONIZATION OF SYSTEM RESOURCES IN A MULTI-SOCKET DATA PROCESSING SYSTEM
    3.
    发明公开
    SYNCHRONIZATION OF SYSTEM RESOURCES IN A MULTI-SOCKET DATA PROCESSING SYSTEM 审中-公开

    公开(公告)号：US20230153156A1

    公开(公告)日：2023-05-18

    申请号：US17455074

    申请日：2021-11-16

    申请人： Xilinx, Inc.

    发明人： Karthik Shankar ,  Jaideep Dastidar ,  Ahmad R. Ansari ,  Sagheer Ahmad

    IPC分类号： G06F9/50

    CPC分类号： G06F9/5027

    摘要： Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

    Logical transport overlayed over a physical transport having a tree topology
    4.
    发明授权
    Logical transport overlayed over a physical transport having a tree topology 有权

    公开(公告)号：US11563639B1

    公开(公告)日：2023-01-24

    申请号：US16025762

    申请日：2018-07-02

    申请人： Xilinx, Inc.

    发明人： Millind Mittal ,  Jaideep Dastidar

    IPC分类号： H04L41/12 ,  H04L41/0803

    摘要： In an example, a system specifies a first configuration of the physical transport network that models a plurality of devices as a corresponding first plurality of nodes having a tree topology. Each node of the first plurality of nodes has at least one first device identifier and at least one first connection identifier to other nodes in the tree topology. The system specifies a second configuration of the logical transport network that models the plurality of devices as the first plurality of nodes having a non-tree topology. Each node of the first plurality of nodes has at least one second device identifier, at least one second connection identifier to other nodes in the non-tree topology, the at least one first device identifier, and the at least one first connection identifier of the tree topology. The system folds the logical transport network over the physical transport network using the at least one second device identifier, at least one second connection identifier to other nodes in the non-tree topology, the at least one first device identifier, and the at least one first connection identifier of the tree topology.

    Cache coherent acceleration function virtualization
    5.
    发明授权
    Cache coherent acceleration function virtualization 有权

    公开(公告)号：US11474871B1

    公开(公告)日：2022-10-18

    申请号：US16582958

    申请日：2019-09-25

    申请人： XILINX, INC.

    发明人： Millind Mittal ,  Jaideep Dastidar

    IPC分类号： G06F9/50 ,  G06F12/0815 ,  G06F9/455 ,  G06F9/38

    摘要： The embodiments herein describe a virtualization framework for cache coherent accelerators where the framework incorporates a layered approach for accelerators in their interactions between a cache coherent protocol layer and the functions performed by the accelerator. In one embodiment, the virtualization framework includes a first layer containing the different instances of accelerator functions (AFs), a second layer containing accelerator function engines (AFE) in each of the AFs, and a third layer containing accelerator function threads (AFTs) in each of the AFEs. Partitioning the hardware circuitry using multiple layers in the virtualization framework allows the accelerator to be quickly re-provisioned in response to requests made by guest operation systems or virtual machines executing in a host. Further, using the layers to partition the hardware permits the host to re-provision sub-portions of the accelerator while the remaining portions of the accelerator continue to operate as normal.

    Multiple protocol layer conversion
    6.
    发明授权
    Multiple protocol layer conversion 有权

    公开(公告)号：US11375050B1

    公开(公告)日：2022-06-28

    申请号：US17019039

    申请日：2020-09-11

    申请人： XILINX, INC.

    发明人： Millind Mittal ,  Jaideep Dastidar ,  Kiran Puranik

    IPC分类号： H04L69/18

    摘要： Embodiments herein describe a layer converter that includes a proxy legacy interface that permits the layers for a legacy interconnect protocol to be recycled without any modifications, thus achieving legacy functionality alongside the new protocols' layer implementation. Put differently, the layer converter permits the layers of the legacy interconnect protocol to be reused to permit data to be transmitted on a link shared with data transmitted using a new interconnect protocol.

    Producer-to-consumer active direct cache transfers
    7.
    发明授权
    Producer-to-consumer active direct cache transfers 有权

    公开(公告)号：US11113194B2

    公开(公告)日：2021-09-07

    申请号：US16560217

    申请日：2019-09-04

    申请人： XILINX, INC.

    发明人： Jaideep Dastidar ,  Millind Mittal

    IPC分类号： G06F12/0811 ,  G06F12/0804 ,  G06F12/121

    摘要： The embodiments herein creates DCT mechanisms that initiate a DCT at the time the updated data is being evicted from the producer cache. These DCT mechanisms are applied when the producer is replacing the updated contents in its cache because the producer has either moved on to working on a different data set (e.g., a different task) or moved on to working on a different function, or when the producer-consumer task manager (e.g., a management unit) enforces software coherency by sending Cache Maintenance Operations (CMO). One advantage of the DCT mechanism is that because the direct cache transfer takes place at the time the updated data is being evicted, by the time the consumer begins its task, the updated contents have already been placed in its own cache or another cache within the cache hierarchy.

    HYBRID PRECISE AND IMPRECISE CACHE SNOOP FILTERING
    9.
    发明申请
    HYBRID PRECISE AND IMPRECISE CACHE SNOOP FILTERING 审中-公开

    公开(公告)号：US20200042446A1

    公开(公告)日：2020-02-06

    申请号：US16053488

    申请日：2018-08-02

    申请人： Xilinx, Inc.

    发明人： Millind Mittal ,  Jaideep Dastidar

    IPC分类号： G06F12/0815

    摘要： Circuits and methods for combined precise and imprecise snoop filtering. A memory and a plurality of processors are coupled to the interconnect circuitry. A plurality of cache circuits are coupled to the plurality of processor circuits, respectively. A first snoop filter is coupled to the interconnect and is configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory. A second snoop filter is coupled to the interconnect and is configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory. Each group encompasses a plurality of cache lines.

    Multi-tenant aware data processing units
    10.
    发明授权
    Multi-tenant aware data processing units 有权

    公开(公告)号：US12086083B2

    公开(公告)日：2024-09-10

    申请号：US17892989

    申请日：2022-08-22

    申请人： XILINX, INC.

    发明人： Jaideep Dastidar ,  David James Riddoch

    IPC分类号： G06F13/20

    CPC分类号： G06F13/20 ,  G06F2213/40

    摘要： Embodiments herein describe creating tag bindings that can be used to assign tags to data corresponding to different tenants using a data processing unit (DPU) such as a SmartNIC, Artificial Intelligence Unit, Network Storage Unit, Database Acceleration Units, and the like. In one embodiment, the DPUs include tag gateways at the interface between a host and network element (e.g., a switch) that recognize and tag the data corresponding to the tenants. These tags are then recognized by data processing engines (DPEs) in the DPU such as AI engines, cryptographic engines, encryption engines, Direct Memory Access (DMA) engines, and the like. These DPEs can be configured to perform tag policies that provide security isolation and performance isolation between the tenants.