公开(公告)号：US20240311239A1

公开(公告)日：2024-09-19

申请号：US18679341

申请日：2024-05-30

申请人： Micron Technology, Inc.

发明人： Gil Golov

IPC分类号： G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F12/0804 ,  G11C11/406 ,  G11C29/42 ,  G11C29/52 ,  H03M13/09 ,  H03M13/11

CPC分类号： G06F11/1068 ,  G06F12/0804 ,  G11C29/52 ,  G06F3/0656 ,  G06F11/073 ,  G06F11/1052 ,  G06F2212/1032 ,  G06F2212/608 ,  G11C11/40607 ,  G11C29/42 ,  G11C2207/2245 ,  G11C2211/4062 ,  H03M13/098 ,  H03M13/11

摘要： A deferred error correction code (ECC) scheme for memory devices is disclosed. A disclosed method includes starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.

公开(公告)号：US11961588B2

公开(公告)日：2024-04-16

申请号：US17590528

申请日：2022-02-01

申请人： Micron Technology, Inc.

发明人： Corrado Villa

IPC分类号： G11C8/16 ,  G11C7/04 ,  G11C7/10 ,  G11C8/10 ,  G11C29/18

CPC分类号： G11C8/16 ,  G11C7/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/10 ,  G11C2029/1804 ,  G11C2207/2245

摘要： Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

公开(公告)号：US11886538B2

公开(公告)日：2024-01-30

申请号：US18091002

申请日：2022-12-29

申请人： Lodestar Licensing Group, LLC

发明人： Jeremiah James Willcock

IPC分类号： G06F7/00 ,  G06F17/18 ,  G06T5/40 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G06V10/50 ,  G06V10/94

CPC分类号： G06F17/18 ,  G06F7/00 ,  G06T5/40 ,  G06V10/50 ,  G06V10/955 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/2245

摘要： A processor-in-memory device includes a memory array, a sense amplifier, and a processing unit that has an accumulator. The processing unit is configured to receive a set of data. The processing unit then uses the sense amplifier and the accumulator to generate a first histogram of the set of data.

公开(公告)号：US11842762B2

公开(公告)日：2023-12-12

申请号：US17439215

申请日：2020-03-16

申请人： RAMBUS INC.

发明人： Frederick Ware ,  Thomas Vogelsang ,  Michael Raymond Miller ,  Collins Williams

IPC分类号： G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408

CPC分类号： G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2207/2245

摘要： Disclosed is a memory system that has a memory controller and may have a memory component. The memory component may be a dynamic random access memory (DRAM). The memory controller is connectable to the memory component. The memory component has at least one data row and at least one tag row different from and associated with the at least one data row. The memory system is to implement a cache having multiple ways to hold a data group. The memory controller is operable in each of a plurality of operating modes. The operating modes include a first operating mode and a second operating mode. The first operating mode and the second operating mode have differing addressing and timing for accessing the data group. The memory controller has cache read logic that sends a cache read command, cache results logic that receives a response from the memory component, and cache fetch logic.

公开(公告)号：US11797225B2

公开(公告)日：2023-10-24

申请号：US17958915

申请日：2022-10-03

申请人： Lodestar Licensing Group, LLC

发明人： George Pax ,  Jonathan Scott Parry

IPC分类号： G06F11/00 ,  G06F3/06 ,  G06F12/02 ,  G11C5/04 ,  G11C7/22 ,  G11C16/32 ,  G06F11/10 ,  G11C29/00 ,  G11C11/00 ,  G11C5/14 ,  G11C7/10 ,  G11C8/00 ,  G11C29/52 ,  G11C29/04

CPC分类号： G06F3/0656 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G11C5/04 ,  G11C5/141 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/005 ,  G11C16/32 ,  G11C29/52 ,  G11C29/883 ,  G06F2212/1032 ,  G06F2212/7202 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2207/2245

摘要： Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

公开(公告)号：US11693561B2

公开(公告)日：2023-07-04

申请号：US17829850

申请日：2022-06-01

申请人： Micron Technology, Inc.

发明人： Perry V. Lea ,  Glen E. Hush

IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097

CPC分类号： G06F3/061 ,  G06F3/0635 ,  G06F3/0665 ,  G06F3/0689 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1009 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/2245

摘要： The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.

公开(公告)号：US20190213136A1

公开(公告)日：2019-07-11

申请号：US16359514

申请日：2019-03-20

申请人： Everspin Technologies, Inc.

发明人： Thomas S. ANDRE ,  Syed M. ALAM ,  Chitra K. SUBRAMANIAN ,  Javed S. BARKATULLAH

IPC分类号： G06F12/0893 ,  G06F3/06 ,  G06F12/0862 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32 ,  G11C11/16 ,  G06F12/02 ,  G06F12/0802

CPC分类号： G06F12/0893 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0215 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2024 ,  G06F2212/3042 ,  G06F2212/6026 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/1693 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2207/2272 ,  Y02D10/13

摘要： A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US20180268893A1

公开(公告)日：2018-09-20

申请号：US15916427

申请日：2018-03-09

申请人： Toshiba Memory Corporation

发明人： Keiji Ikeda ,  Chika Tanaka ,  Toshinori Numata ,  Tsutomu Tezuka

IPC分类号： G11C11/406 ,  G11C11/403 ,  G11C11/4094

CPC分类号： G11C11/40607 ,  G11C11/403 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4085 ,  G11C11/4094 ,  G11C2207/2245

摘要： According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.

公开(公告)号：US20180211708A1

公开(公告)日：2018-07-26

申请号：US15876923

申请日：2018-01-22

申请人： Toshiba Memory Corporation

发明人： Shunichi IGAHARA ,  Toshikatsu HIDA

IPC分类号： G11C16/10 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G11C16/08

CPC分类号： G11C16/105 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7202 ,  G06F2212/7211 ,  G11C7/1096 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3495 ,  G11C2207/2209 ,  G11C2207/2245 ,  G11C2211/5641

摘要： A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.

公开(公告)号：US09996280B2

公开(公告)日：2018-06-12

申请号：US15071100

申请日：2016-03-15

申请人： SanDisk Technologies, Inc.

发明人： Jingwen Ouyang

IPC分类号： G06F3/06 ,  G11C16/10 ,  G11C16/32

CPC分类号： G06F3/0619 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0688 ,  G11C16/10 ,  G11C16/32 ,  G11C2207/2245

摘要： Apparatuses, systems, methods, and computer program products are disclosed for data register copying for a non-volatile storage array. An apparatus may include an array of non-volatile storage cells. A set of write buffer data registers may be configured to store target data for a program operation for an array. Write buffer data registers may communicate target data to corresponding columns of an array. A set of shadow data registers may be configured to receive target data from peripheral circuitry for an array. A portion of target data received by a shadow data register may be copied to a corresponding write buffer data register while the shadow data register receives the portion of the target data.