公开(公告)号：US09838011B2

公开(公告)日：2017-12-05

申请号：US14405881

申请日：2014-04-01

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Rifeng Mai

IPC: H03K17/16 ,  H03K19/00 ,  G11C29/02 ,  G11C29/50 ,  H03K17/687 ,  G11C7/10

CPC classification number: H03K19/0005 ,  G11C7/1057 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254 ,  H03K17/6872

Abstract: An integrated circuit chip includes at least one driver circuit of single-ended structure and the first drive circuit, the first drive circuit and the at least one driver circuit of single-ended structure have the same structure, the first drive circuit includes a plurality of parallel-connected PMOS tubes and a plurality of parallel-connected NMOS tubes, the plurality of parallel-connected PMOS tubes connect the plurality of parallel-connected NMOS tube in series at a first node. After impedance calibration has been conducted, the chip confines a first impedance calibration code and a second impedance calibration code, and controls the at least one driver according to the first impedance calibration code and the second impedance calibration code; the first reference voltage is preferably configured to ¾ times of the supply voltage VDD, and the second reference voltage is preferably configured to ¼ times of the supply voltage VDD.

公开(公告)号：US09754644B2

公开(公告)日：2017-09-05

申请号：US14758357

申请日：2014-12-30

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Yuanpeng Wang ,  Ping Fan ,  Jia Geng

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G11C8/18 ,  G11C8/06

CPC classification number: G11C7/109 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/1776

Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.

公开(公告)号：US09590633B2

公开(公告)日：2017-03-07

申请号：US14761403

申请日：2014-12-11

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Ping Fan ,  Jia Geng ,  Yuanpeng Wang

IPC: G06F7/38 ,  H03K19/173 ,  G06F7/501

CPC classification number: H03K19/1737 ,  G06F7/501 ,  G06F7/506 ,  H03K19/1733

Abstract: A carry-skip one-bit full adder and a field programmable gate array device, the full adder includes: a first multiplexer, a second multiplexer, and an adder, the first multiplexer includes a first addend input end and a first constant input end configured to input a first constant to the first multiplexer; the second multiplexer includes a second addend input end and a second constant input end configured to input a second constant to the second multiplexer; when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input, and the second multiplexer selects to output the second constant input.

Abstract translation: 一种进位跳跃一比特全加器和现场可编程门阵列器件，全加器包括：第一多路复用器，第二多路复用器和加法器，第一多路复用器包括第一加法输入端和配置的第一恒定输入端 以向第一多路复用器输入第一常数; 第二多路复用器包括第二加数输入端和被配置为向第二多路复用器输入第二常数的第二恒定输入端; 当第一加数输入端不用于第一加数的输入时，和/或当第二加数输入端不用于第二加数的输入时，第一多路复用器选择输出第一常数输入，第二多路复用器 选择输出第二个常数输入。

公开(公告)号：US20160322084A1

公开(公告)日：2016-11-03

申请号：US14758357

申请日：2014-12-30

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Yuanpeng WANG ,  Ping FAN ,  Jia GENG

IPC: G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  G11C7/22 ,  G11C8/10

CPC classification number: G11C7/109 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/1776

Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.

Abstract translation: 可扩展的可配置FPGA存储结构和FPGA器件，其中FPGA存储结构包括：多个本地存储单元，控制器和两个时钟缓冲器，其中两个时钟缓冲器分别用于为两个时钟输入端口提供不同的时钟信号 的控制器; 控制器用于接收外部输入的写入地址信号，并由时钟信号驱动，产生多个使能信号和写入地址解码信号以输出到多个本地存储单元; 并且每个本地存储单元包括本地存储器和用于为本地存储器提供输入数据的多路复用器; 并且基于每个本地存储单元的配置模式，根据使能信号，输入写地址解码信号或读地址信号以及输入数据，生成相应配置模式的输出数据。

公开(公告)号：US20160315620A1

公开(公告)日：2016-10-27

申请号：US14761429

申请日：2014-12-11

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Ping FAN ,  Jia GENG ,  Yuanpeng WANG

IPC: H03K19/177 ,  G06F7/501 ,  H03K19/173

CPC classification number: H03K19/17728 ,  G06F7/501 ,  H03K19/1737

Abstract: An extensible and configurable logic element, wherein the logic element includes: multiple logic parcels, each logic parcel includes two logic cells; each logic cell includes seven inputs, three outputs, an addition carry input, an addition carry output, a six-input and two-output look-up table, a one bit full adder, a first register, and a second register; wherein, the first register stores a signal output by the first output of the look-up table or a carry signal of the full adder according to the configuration; the second register stores a signal output by the second output of the look-up table or an output signal of the full adder according to the configuration; the addition carry output in the current logic cell is connected to the addition carry input in the higher logic cell of the current logic cell, including an addition carry chain in the logic element.

Abstract translation: 一种可扩展和可配置的逻辑元件，其中所述逻辑元件包括：多个逻辑宗地，每个逻辑宗地包括两个逻辑单元; 每个逻辑单元包括七个输入，三个输出，加法进位输入，加法进位输出，六输入和双输出查询表，一位全加器，第一寄存器和第二寄存器; 其中，所述第一寄存器根据所述配置存储由所述查找表的第一输出或全加器的进位信号输出的信号; 第二寄存器根据该配置存储由查找表的第二输出端输出的信号或全加器的输出信号; 当前逻辑单元中的加法进位输出连接到当前逻辑单元的较高逻辑单元中的加法进位输入，包括逻辑元件中的加法进位链。

公开(公告)号：US20160285619A1

公开(公告)日：2016-09-29

申请号：US14405044

申请日：2014-04-22

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Rifeng MAI

IPC: H04L7/04 ,  H04L7/033

CPC classification number: H04L7/04 ,  H03L7/0996 ,  H04L7/0012 ,  H04L7/0331 ,  H04L7/0337

Abstract: An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

Abstract translation: LVDS数据恢复方法包括采用三个时钟同时采样接收的信号时钟，其中第一时钟，第二时钟和第三时钟具有相同的频率和不同的相位; 根据同时由三个时钟采样的接收信号时钟的采样电平，确定第一时钟是否处于接收信号时钟的上升沿; 在确定第一时钟处于接收信号时钟的上升沿之后，调整第一时钟的相位，并且根据第一时钟的调整相位对接收到的数据信号进行采样。 LVDS数据恢复方法确保采样时钟沿与被采样数据的中心对齐。 在高速的情况下，数据采样的准确性得到保证。

公开(公告)号：US09787468B2

公开(公告)日：2017-10-10

申请号：US14405044

申请日：2014-04-22

Applicant: Capital Microelectronics Co., Ltd.

Inventor： Rifeng Mai

IPC: H04L7/04 ,  H04L7/033 ,  H04L7/00 ,  H03L7/099

CPC classification number: H04L7/04 ,  H03L7/0996 ,  H04L7/0012 ,  H04L7/0331 ,  H04L7/0337

Abstract: An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

公开(公告)号：US20170168842A1

公开(公告)日：2017-06-15

申请号：US15026824

申请日：2015-07-21

Applicant: Capital Microelectronics co., Ltd.

Inventor： Xian YANG ,  Qinghua XUE

IPC: G06F9/44 ,  G06F12/06

Abstract: A circuit and method of power on initialization for a configuration memory of an FPGA. The circuit includes: a decoding circuit, a driving circuit, and a configuration memory, where when 0 is written for the 1st time, the decoding circuit turns on a word line corresponding to an address in the configuration memory, and the driving circuit writes content of the word line into 0; and when 0 is written for the ith time, the decoding circuit turns on at least one word line corresponding to at least one address in the configuration memory, and the driving circuit writes content of each word line in the at least one word line into 0, the number of the at least one address being less than or equal to a sum of addresses that have completed writing of 0 for the previous (i−1)th time.

公开(公告)号：US20160315619A1

公开(公告)日：2016-10-27

申请号：US14761410

申请日：2014-12-11

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Ping FAN ,  Jia GENG ,  Yuanpeng WANG

IPC: H03K19/177 ,  H03K19/00 ,  H03K19/173

CPC classification number: H03K19/17728 ,  H03K19/0008 ,  H03K19/1732 ,  H03K19/1737 ,  H03K19/17776

Abstract: A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.

Abstract translation: 多模支持和可配置的六输入查找表（LUT）的结构以及现场可编程门阵列（FPGA）装置。 六输入LUT具有六个信号输入端和两个信号输出端。 六输入LUT包括：第一五输入LUT，第二五输入LUT，第一多路复用器和第二多路复用器。 第一五输入LUT根据六输入LUT的五个信号输入端输入的五个数据信号输出第一输出信号，其中第一输出信号由六输入LUT的第一信号输出端输出; 第二五输入LUT根据由六输入LUT的五个信号输入端输入的五个数据信号输出第二输出信号; 并且所述第一多路复用器根据设定的配置模式输出控制信号，以控制所述第二多路复用器输出所述第一输出信号或所述第二输出信号。

公开(公告)号：US20160261264A1

公开(公告)日：2016-09-08

申请号：US14389407

申请日：2014-03-19

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Rifeng MAI

IPC: H03K17/22 ,  H03K3/037 ,  H03K17/284

CPC classification number: H03K17/223 ,  G06F1/24 ,  G06F1/26 ,  H03K3/0377 ,  H03K17/284

Abstract: A power-on reset (POR) circuit includes an RC circuit; a Schmitt trigger, an inverter, and a first PMOS tube. A power supply voltage charges a capacitor through the RC circuit. When a voltage of the capacitor reaches a first threshold, the Schmitt trigger reverses, a first level is output. The POR circuit includes a discharge circuit used to detect a glitch of the power supply voltage, and output a first signal to an input end of the Schmitt trigger when the glitch is detected. The first signal allows the Schmitt trigger to reverse again to output a second level, so as to turn off the first PMOS tube through the inverting amplifier. When the power supply voltage rises along an oblique line again, the Schmitt trigger reverses, and the first level is output, so as to reset the system where the circuit is.

Abstract translation: 上电复位（POR）电路包括RC电路; 施密特触发器，反相器和第一PMOS管。 电源电压通过RC电路对电容器充电。 当电容器的电压达到第一阈值时，施密特触发器反相，输出第一电平。 POR电路包括用于检测电源电压毛刺的放电电路，并且当检测到毛刺时，将第一信号输出到施密特触发器的输入端。 第一个信号允许施密特触发器再次反转以输出第二电平，以便通过反相放大器关闭第一个PMOS管。 当电源电压再次沿斜线上升时，施密特触发器反向，并输出第一电平，以便重新设置电路的系统。