公开(公告)号：US09727415B2

公开(公告)日：2017-08-08

申请号：US14772455

申请日：2014-11-27

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Jia Geng ,  Yuanpeng Wang ,  Ping Fan

IPC: H03M13/00 ,  G06F11/10 ,  G11C7/10 ,  G06F3/06 ,  G11C29/52 ,  H03M13/29 ,  G06F5/10 ,  H03M13/05 ,  H03M13/19 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/064 ,  G06F3/0679 ,  G06F5/10 ,  G06F11/1028 ,  G06F11/1048 ,  G11C7/10 ,  G11C7/1075 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/19 ,  H03M13/2906

Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.

公开(公告)号：US09754644B2

公开(公告)日：2017-09-05

申请号：US14758357

申请日：2014-12-30

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Yuanpeng Wang ,  Ping Fan ,  Jia Geng

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G11C8/18 ,  G11C8/06

CPC classification number: G11C7/109 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/1776

Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.

公开(公告)号：US09590633B2

公开(公告)日：2017-03-07

申请号：US14761403

申请日：2014-12-11

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Ping Fan ,  Jia Geng ,  Yuanpeng Wang

IPC: G06F7/38 ,  H03K19/173 ,  G06F7/501

CPC classification number: H03K19/1737 ,  G06F7/501 ,  G06F7/506 ,  H03K19/1733

Abstract: A carry-skip one-bit full adder and a field programmable gate array device, the full adder includes: a first multiplexer, a second multiplexer, and an adder, the first multiplexer includes a first addend input end and a first constant input end configured to input a first constant to the first multiplexer; the second multiplexer includes a second addend input end and a second constant input end configured to input a second constant to the second multiplexer; when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input, and the second multiplexer selects to output the second constant input.

Abstract translation: 一种进位跳跃一比特全加器和现场可编程门阵列器件，全加器包括：第一多路复用器，第二多路复用器和加法器，第一多路复用器包括第一加法输入端和配置的第一恒定输入端 以向第一多路复用器输入第一常数; 第二多路复用器包括第二加数输入端和被配置为向第二多路复用器输入第二常数的第二恒定输入端; 当第一加数输入端不用于第一加数的输入时，和/或当第二加数输入端不用于第二加数的输入时，第一多路复用器选择输出第一常数输入，第二多路复用器 选择输出第二个常数输入。

公开(公告)号：US09584128B2

公开(公告)日：2017-02-28

申请号：US14761410

申请日：2014-12-11

Applicant: CAPITAL MICROELECTRONICS CO., LTD.

Inventor： Ping Fan ,  Jia Geng ,  Yuanpeng Wang

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/00

CPC classification number: H03K19/17728 ,  H03K19/0008 ,  H03K19/1732 ,  H03K19/1737 ,  H03K19/17776

Abstract: A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.

Abstract translation: 多模支持和可配置的六输入查找表（LUT）的结构以及现场可编程门阵列（FPGA）装置。 六输入LUT具有六个信号输入端和两个信号输出端。 六输入LUT包括：第一五输入LUT，第二五输入LUT，第一多路复用器和第二多路复用器。 第一五输入LUT根据六输入LUT的五个信号输入端输入的五个数据信号输出第一输出信号，其中第一输出信号由六输入LUT的第一信号输出端输出; 第二五输入LUT根据由六输入LUT的五个信号输入端输入的五个数据信号输出第二输出信号; 并且所述第一多路复用器根据设定的配置模式输出控制信号，以控制所述第二多路复用器输出所述第一输出信号或所述第二输出信号。