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    HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATION SCHEME
    1.
    发明申请
    HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATION SCHEME 审中-公开

    公开(公告)号：US20190156873A1

    公开(公告)日：2019-05-23

    申请号：US16194991

    申请日：2018-11-19

    Applicant: Altera Corporation

    Inventor： Jun Pin Tan ,  Kiun Kiet Jong ,  Lai Pheng Tan

    IPC: G11C8/04 ,  H03K19/177 ,  G06F9/4401 ,  G11C7/00 ,  G11C7/10

    Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

    Techniques For Storing States Of Signals In Configurable Storage Circuits
    2.
    发明公开
    Techniques For Storing States Of Signals In Configurable Storage Circuits 审中-公开

    公开(公告)号：US20240137026A1

    公开(公告)日：2024-04-25

    申请号：US18397673

    申请日：2023-12-27

    Applicant: Altera Corporation

    Inventor： Bee Yee Ng ,  Ilya Ganusov ,  Jun Pin Tan

    IPC: H03K19/17728 ,  G01R31/3185

    CPC classification number: H03K19/17728 ,  G01R31/318586

    Abstract: An integrated circuit includes a logic circuit block that includes a first adaptive logic module configurable to store a first state of a first signal received from a device-under-test in a first register, a second adaptive logic module configurable to store a second state of a second signal in a second register during a user mode of the integrated circuit simultaneously with the first state of the first signal being stored in the first register, and a third adaptive logic module configurable to store a third state of the first signal in a third register. The first and the third states of the first signal are stored for consecutive clock cycles in the first register and the third register. The logic circuit block is configurable to scan out the second state in the second register and the third state in the third register.

    High speed FPGA boot-up through concurrent multi-frame configuration scheme
    3.
    发明授权
    High speed FPGA boot-up through concurrent multi-frame configuration scheme 有权

    公开(公告)号：US10186305B2

    公开(公告)日：2019-01-22

    申请号：US15489535

    申请日：2017-04-17

    Applicant: ALTERA CORPORATION

    Inventor： Jun Pin Tan ,  Kiun Kiet Jong ,  Lai Pheng Tan

    IPC: G06F7/38 ,  H03K19/177 ,  G11C8/04 ,  G11C7/10 ,  G11C7/00 ,  G06F9/4401

    Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

    Integrated circuit with state and data retention
    4.
    发明授权
    Integrated circuit with state and data retention 有权
    具有状态和数据保持的集成电路

    公开(公告)号：US09383802B1

    公开(公告)日：2016-07-05

    申请号：US13922649

    申请日：2013-06-20

    Applicant: Altera Corporation

    Inventor： Jun Pin Tan ,  Kiun Kiet Jong

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/3203

    Abstract: A method of operating an integrated circuit that includes a plurality of registers may include receiving a sleep mode request for the integrated circuit. The sleep mode request may be a control signal received with control circuitry on the integrated circuit. The plurality of registers may be configured to operate as a scan chain when the sleep mode request is received. Integrated circuit state information that are stored in the plurality of registers may be retrieved by operating the scan chain and stored in a memory module. The integrated circuit may be placed in a sleep mode. Placing the integrated circuit in the sleep mode may reduce power consumption of the integrated circuit.

    Abstract translation: 一种操作包括多个寄存器的集成电路的方法可以包括接收针对集成电路的睡眠模式请求。 睡眠模式请求可以是与集成电路上的控制电路一起接收的控制信号。 多个寄存器可被配置为当接收到睡眠模式请求时作为扫描链操作。 可以通过操作扫描链并存储在存储器模块中来检索存储在多个寄存器中的集成电路状态信息。 集成电路可以被置于睡眠模式。 将集成电路置于睡眠模式可能会降低集成电路的功耗。

    HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATION SCHEME
    5.
    发明申请
    HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATION SCHEME 审中-公开
    高速FPGA通过并联多帧配置方案启动

    公开(公告)号：US20160307612A1

    公开(公告)日：2016-10-20

    申请号：US15197356

    申请日：2016-06-29

    Applicant: ALTERA CORPORATION

    Inventor： Jun Pin Tan ,  Kiun Kiet Jong ,  Lai Pheng Tan

    IPC: G11C8/04 ,  G11C7/00

    CPC classification number: G11C8/04 ,  G06F9/4403 ,  G11C7/00 ,  G11C7/1039 ,  H03K19/1776 ,  H03K19/17776

    Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

    Abstract translation: 本文提供了用于实现可编程集成电路器件的系统和方法，其通过显着减少配置时间来实现高速FPGA引导。 通过启用高速FPGA启动，可编程集成电路器件将能够适应需要比常规可编程集成电路器件能够容纳的更快启动时间的应用。 为了实现高速引导，为数据线的每个数据线段实现专用地址寄存器，这又大大减少了配置随机存取存储器（CRAM）写入时间（例如，至少两倍） ）。

    CONFIGURING DATA REGISTERS TO PROGRAM A PROGRAMMABLE DEVICE WITH A CONFIGURATION BIT STREAM WITHOUT PHANTOM BITS
    6.
    发明申请
    CONFIGURING DATA REGISTERS TO PROGRAM A PROGRAMMABLE DEVICE WITH A CONFIGURATION BIT STREAM WITHOUT PHANTOM BITS 有权
    配置数据寄存器来编程具有不带有PHANTOM位的配置位流的可编程器件

    公开(公告)号：US20140240000A1

    公开(公告)日：2014-08-28

    申请号：US13780526

    申请日：2013-02-28

    Applicant: ALTERA CORPORATION

    Inventor： Jun Pin Tan ,  Kiun Kiet Jong

    IPC: H03K19/0175

    CPC classification number: H03K19/017581

    Abstract: Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.

    Abstract translation: 技术和机制在诸如可编程逻辑器件（PLD）之类的电路中动态地配置组成数据寄存器的寄存器之间的移位寄存器。 用于配置PLD的配置比特流可以具有减小的大小，如果不对应于配置元素的“幻像位”被去除。 可以动态地配置移位寄存器，使得可以跳过不对应于物理配置元件的寄存器。 因此，PLD可以用没有幻像位的配置位流进行编程。

    High speed FPGA boot-up through concurrent multi-frame configuration scheme
    8.
    发明授权
    High speed FPGA boot-up through concurrent multi-frame configuration scheme 有权
    通过并发多帧配置方案实现高速FPGA启动

    公开(公告)号：US09401190B1

    公开(公告)日：2016-07-26

    申请号：US14685098

    申请日：2015-04-13

    Applicant: Altera Corporation

    Inventor： Jun Pin Tan ,  Kiun Kiet Jong ,  Lai Pheng Tan

    IPC: G06F7/38 ,  H03K19/177 ,  G11C8/04 ,  G11C7/00

    CPC classification number: G11C8/04 ,  G06F9/4403 ,  G11C7/00 ,  G11C7/1039 ,  H03K19/1776 ,  H03K19/17776

    Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

    Abstract translation: 本文提供了用于实现可编程集成电路器件的系统和方法，其通过显着减少配置时间来实现高速FPGA引导。 通过启用高速FPGA启动，可编程集成电路器件将能够适应需要比常规可编程集成电路器件能够容纳的更快启动时间的应用。 为了实现高速引导，为数据线的每个数据线段实现专用地址寄存器，这又大大减少了配置随机存取存储器（CRAM）写入时间（例如，至少两倍） ）。

    Configuring data registers to program a programmable device with a configuration bit stream without phantom bits
    9.
    发明授权
    Configuring data registers to program a programmable device with a configuration bit stream without phantom bits 有权
    配置数据寄存器以编程具有不带幻像位的配置位流的可编程器件

    公开(公告)号：US08941408B2

    公开(公告)日：2015-01-27

    申请号：US13780526

    申请日：2013-02-28

    Applicant: Altera Corporation

    Inventor： Jun Pin Tan ,  Kiun Kiet Jong

    IPC: H03K19/177 ,  G06M3/00 ,  H03K19/0175

    CPC classification number: H03K19/017581

    Abstract: Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.

    Abstract translation: 技术和机制在诸如可编程逻辑器件（PLD）之类的电路中动态地配置组成数据寄存器的寄存器之间的移位寄存器。 用于配置PLD的配置比特流可以具有减小的大小，如果不对应于配置元素的“幻像位”被去除。 可以动态地配置移位寄存器，使得可以跳过不对应于物理配置元件的寄存器。 因此，PLD可以用没有幻像位的配置位流进行编程。

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