公开(公告)号：US12072802B2

公开(公告)日：2024-08-27

申请号：US18152642

申请日：2023-01-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/7203

Abstract: A hybrid memory includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

公开(公告)号：US12067293B2

公开(公告)日：2024-08-20

申请号：US17746019

申请日：2022-05-17

Applicant: Western Digital Technologies, Inc.

Inventor： Amit Sharma ,  Dinesh Kumar Agarwal ,  Abhinandan Venugopal

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0688 ,  G06F2212/7203

Abstract: A data storage device and method are provided for host multi-command queue grouping based on write-size alignment in a multi-queue-depth environment. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to provide a host with an indication of a required amount of data needed to program a set of multi-level cell blocks in the memory; receive an assurance from the host that the host will be providing the data storage device with the required amount of data; and based on the assurance received from the host, program the set of multi-level cell blocks as data is received from the host but before the required amount of data is received from the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

公开(公告)号：US20240248601A1

公开(公告)日：2024-07-25

申请号：US18623811

申请日：2024-04-01

Applicant: Lodestar Licensing Group LLC

Inventor： Robert M. Walker ,  James A. Hall, JR.

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0605 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/261 ,  G06F2212/7203 ,  G06F2212/7207

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.

公开(公告)号：US11947796B2

公开(公告)日：2024-04-02

申请号：US17749801

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  James A. Hall, Jr.

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0605 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/261 ,  G06F2212/7203 ,  G06F2212/7207

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.

公开(公告)号：US11907127B2

公开(公告)日：2024-02-20

申请号：US17739033

申请日：2022-05-06

Applicant: SMART IOPS, INC.

Inventor： Ashutosh Kumar Das ,  Manuel Antonio d'Abreu

IPC: G06F12/0871 ,  G06F12/0804 ,  G06F12/06 ,  G06F12/0893 ,  G06F12/02

CPC classification number: G06F12/0871 ,  G06F12/0246 ,  G06F12/0661 ,  G06F12/0804 ,  G06F12/0893 ,  G06F2212/2024 ,  G06F2212/284 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7206

Abstract: In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.

公开(公告)号：US11868257B2

公开(公告)日：2024-01-09

申请号：US17860263

申请日：2022-07-08

Applicant: Western Digital Technologies, Inc.

Inventor： Shay Benisty

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0804 ,  G06F3/06 ,  G06F12/0868 ,  G06F12/0855 ,  G06F12/0871

CPC classification number: G06F12/0815 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0804 ,  G06F12/0855 ,  G06F12/0868 ,  G06F12/0871 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/1056 ,  G06F2212/214 ,  G06F2212/312 ,  G06F2212/7203

Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.

公开(公告)号：US11797180B2

公开(公告)日：2023-10-24

申请号：US17132539

申请日：2020-12-23

Applicant: Memory Technologies LLC

Inventor： Kimmo J. Mylly ,  Jani J. Klint ,  Jani Hyvonen ,  Tapio Hill ,  Jukka-Pekka Vihmalo ,  Matti Floman

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/10

CPC classification number: G06F3/0607 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/1072 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7206 ,  Y02D10/00

Abstract: A method includes, in one non-limiting embodiment, receiving a command originating from an initiator at a controller associated with a non-volatile mass memory coupled with a host device, the command being a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory; moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory; and acknowledging to the initiator that the command to write the data to the non-volatile mass memory has been executed. An apparatus configured to perform the method is also described.

公开(公告)号：US11740797B2

公开(公告)日：2023-08-29

申请号：US17893118

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  James A. Hall, Jr. ,  Frank F. Ross

IPC: G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F13/1626 ,  G06F2212/1024 ,  G06F2212/7203 ,  G06F2212/7208

Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

公开(公告)号：US11740794B2

公开(公告)日：2023-08-29

申请号：US17527851

申请日：2021-11-16

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Tokumasa Hara

IPC: G06F3/06 ,  G11C7/10 ,  G06F12/0875 ,  G06F13/16 ,  G11C16/10 ,  G11C16/26 ,  G11C7/24

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0875 ,  G06F13/16 ,  G11C7/1063 ,  G11C16/10 ,  G11C16/26 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/452 ,  G06F2212/7203 ,  G06F2212/7207 ,  G11C7/24

Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.

公开(公告)号：US11650758B2

公开(公告)日：2023-05-16

申请号：US17313793

申请日：2021-05-06

Applicant: Western Digital Technologies, Inc.

Inventor： Dattatreya Nayak ,  Arun Kumar Shukla ,  Akash Dungrani

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/60 ,  G06F2212/7203

Abstract: A data storage device and method for host-initiated cached read to recover corrupted data within timeout constraints are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive a read look-ahead command from a host to perform a read look-ahead of a first logical address; receive a read command from the host to read a second logical address; and execute the read look-ahead command by performing the following as background operations while executing the read command: read data for a location in the non-volatile memory that corresponds to the first logical address; correct an error in the data; and cache the corrected data in the volatile memory. The cached corrected data can be sent back to the host in response to the host requesting a read of the same logical address. Other embodiments are provided.