公开(公告)号：US20220261352A1

公开(公告)日：2022-08-18

申请号：US17739033

申请日：2022-05-06

Applicant: SMART IOPS, INC.

Inventor： Ashutosh Kumar Das ,  Manuel Antonio d'Abreu

IPC: G06F12/0871 ,  G06F12/0804 ,  G06F12/06 ,  G06F12/0893 ,  G06F12/02

Abstract: In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.

公开(公告)号：US20210049094A1

公开(公告)日：2021-02-18

申请号：US16996810

申请日：2020-08-18

Applicant: SMART IOPS, INC.

Inventor： Ashutosh Kumar Das ,  Manuel Antonio d'Abreu

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/1045 ,  G06F13/16

Abstract: In certain aspects, dynamic remapping of memory addresses is provided and includes initiating a remapping of a logical block from a “mapped block” to a “remapped block.” Logical address locations for the logical block are mapped to physical address locations in the mapped block. The mapped and remapped blocks include non-volatile memory. A read command is received and determined to be for reading from a logical address location of the logical block, and the logical address location is determined to be mapped to a physical address location. Data is read from the physical address location of the mapped block. A write command is received and determined to be for writing data to the logical address location. Data is written to the physical address location of the remapped block. The read command is received after the initiation of the remapping and before the writing of the data to the remapped block.

公开(公告)号：US20210049104A1

公开(公告)日：2021-02-18

申请号：US16996827

申请日：2020-08-18

Applicant: SMART IOPS, INC.

Inventor： Ashutosh Kumar Das ,  Manuel Antonio D'Abreu

IPC: G06F12/10

Abstract: Devices, systems, and methods are provided that cause a controller to receive a first command to read or write first data from or to a first logical address; and determine a first mapped logical address that the first logical address is mapped to. A first plurality of logical addresses is mapped to the first mapped logical address and includes the first logical address. The controller reads a first data structure at the first mapped logical address. The first data structure includes a pointer to a first intermediate physical address. The controller reads a second data structure at the first intermediate physical address. The second data structure includes a plurality of pointers to target physical addresses. The plurality of pointers includes a pointer to a first target physical address for the first logical address. The controller reads or writes the first data from or to the first target physical address.

公开(公告)号：US20180068701A1

公开(公告)日：2018-03-08

申请号：US15732038

申请日：2017-09-06

Applicant: Smart IOPS, Inc.

Inventor： Manuel Antonio d'Abreu ,  Ashutosh Kumar Das

IPC: G11C8/14 ,  G11B19/02 ,  G11C8/12 ,  H03M13/00

CPC classification number: G11C8/14 ,  G06F11/1044 ,  G11B19/02 ,  G11C7/1006 ,  G11C8/12 ,  G11C16/3495 ,  H03M13/6331

Abstract: In certain aspects, a device may include a memory and a controller coupled to the memory. The controller may be configured to process data to form codewords and to send the codewords to the memory to be stored at locations of the memory. The controller may encode and tag the incoming data (from the host) to minimize the charge that is required to be stored in the non-volatile memory.

公开(公告)号：US12189944B1

公开(公告)日：2025-01-07

申请号：US18348297

申请日：2023-07-06

Applicant: SMART IOPS, INC.

Inventor： Manuel Antonio d'Abreu ,  Ashutosh Kumar Das

IPC: G06F3/00 ,  G06F3/06

Abstract: A solid-state storage device is provided that includes: a controller; non-volatile memory; a device interface; and a protocol-independent interface configured to couple to any one of a plurality of network adapters and communication ports so as to enable the controller to transmit data from the any one of the plurality of network adapters and communication ports. The controller is configured to receive data formatted according to a first protocol from an accessing device via the device interface. The protocol-independent interface includes a plurality of contacts coupled to the controller by a plurality of signal lines that enable data transmission from the controller to the protocol-independent interface. Each of the signal lines of the plurality of signal lines and each of the contacts of the plurality of contacts are configured to be enabled or disabled to form different channels through the protocol-independent interface to accommodate various target protocols.

公开(公告)号：US12164435B2

公开(公告)日：2024-12-10

申请号：US18160225

申请日：2023-01-26

Applicant: SMART IOPS, INC.

Inventor： Ashutosh Kumar Das ,  Manuel Antonio d'Abreu

IPC: G06F12/10

Abstract: Devices, systems, and methods are provided that cause a controller to receive a first command to read or write first data from or to a first logical address; and determine a first mapped logical address that the first logical address is mapped to. A first plurality of logical addresses is mapped to the first mapped logical address and includes the first logical address. The controller reads a first data structure at the first mapped logical address. The first data structure includes a pointer to a first intermediate physical address. The controller reads a second data structure at the first intermediate physical address. The second data structure includes a plurality of pointers to target physical addresses. The plurality of pointers includes a pointer to a first target physical address for the first logical address. The controller reads or writes the first data from or to the first target physical address.

公开(公告)号：US11907127B2

公开(公告)日：2024-02-20

申请号：US17739033

申请日：2022-05-06

Applicant: SMART IOPS, INC.

Inventor： Ashutosh Kumar Das ,  Manuel Antonio d'Abreu

IPC: G06F12/0871 ,  G06F12/0804 ,  G06F12/06 ,  G06F12/0893 ,  G06F12/02

CPC classification number: G06F12/0871 ,  G06F12/0246 ,  G06F12/0661 ,  G06F12/0804 ,  G06F12/0893 ,  G06F2212/2024 ,  G06F2212/284 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7206

Abstract: In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.

公开(公告)号：US11288017B2

公开(公告)日：2022-03-29

申请号：US15904080

申请日：2018-02-23

Applicant: Smart IOPS, Inc.

Inventor： Manuel Antonio d'Abreu ,  Ashutosh Kumar Das

IPC: G06F3/06

Abstract: In certain aspects, a data storage device is provided including a distributed controller configured to communicate with a main controller; and first and second memory devices of respective first and second non-volatile memory technologies. The first and second memory devices are coupled to the distributed controller configured to control access to the first and second memory devices. In certain aspects, a system is provided including a main controller; first and second distributed controllers coupled to the main controller; at least one first memory device coupled to the first distributed controller; and at least one second memory device coupled to the second distributed controller. The main controller is configured to control access to the first and second distributed controllers. The first and second distributed controllers are configured to control access to the respective at least one first and second memory devices that include at least two non-volatile memory technologies.

公开(公告)号：US20180239537A1

公开(公告)日：2018-08-23

申请号：US15904080

申请日：2018-02-23

Applicant: Smart IOPS, Inc.

Inventor： Manuel Antonio d'Abreu ,  Ashutosh Kumar Das

IPC: G06F3/06

CPC classification number: G06F3/067 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/068

Abstract: In certain aspects, a data storage device is provided including a distributed controller configured to communicate with a main controller; and first and second memory devices of respective first and second non-volatile memory technologies. The first and second memory devices are coupled to the distributed controller configured to control access to the first and second memory devices. In certain aspects, a system is provided including a main controller; first and second distributed controllers coupled to the main controller; at least one first memory device coupled to the first distributed controller; and at least one second memory device coupled to the second distributed controller. The main controller is configured to control access to the first and second distributed controllers. The first and second distributed controllers are configured to control access to the respective at least one first and second memory devices that include at least two non-volatile memory technologies.

公开(公告)号：US20200218462A1

公开(公告)日：2020-07-09

申请号：US16824456

申请日：2020-03-19

Applicant: Smart IOPS, Inc.

Inventor： Manuel Antonio d'Abreu ,  Ashutosh Kumar Das

IPC: G06F3/06

Abstract: In some aspects, devices, systems, and methods are provided that relate to data deduplication performed in data storage devices, such as solid-state drives (SSD) or drives of any other type. In some aspects, devices, systems, and methods are provided that relate to hierarchical data deduplication at a local and system level, such as in a storage system built with one or more SSDs having built-in data deduplication functionality. The hierarchical data deduplication utilizes the IDs in the data storage devices to decide if the incoming data has to be stored or if a copy of the incoming data is already stored. In hierarchical data deduplication, no IDs (or signatures) are required to be stored at a system level. In some aspects, data steering is provided that enables data storing coordination in a system that consists of a set of data storage device (e.g., SSDs) having built-in data deduplication.