公开(公告)号：US11990196B2

公开(公告)日：2024-05-21

申请号：US18179434

申请日：2023-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adolf Baumann ,  Mark Jung

IPC: G11C29/36 ,  G11C14/00 ,  G11C5/14

CPC classification number: G11C29/36 ,  G11C14/0063 ,  G11C5/148 ,  G11C2029/3602

Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

公开(公告)号：US10452594B2

公开(公告)日：2019-10-22

申请号：US14887885

申请日：2015-10-20

Applicant: Texas Instruments Incorporated

Inventor： Andreas Waechter ,  Mark Jung ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F13/42 ,  G06F13/28 ,  H04L29/08

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

公开(公告)号：US11755342B2

公开(公告)日：2023-09-12

申请号：US17123407

申请日：2020-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ronald Nerlich ,  Mark Jung ,  Johann Zipperer ,  Dietmar Walther

IPC: G05B1/03 ,  G06F9/448 ,  G06F8/34 ,  G05B19/045

CPC classification number: G06F9/4498 ,  G05B19/045 ,  G06F8/34

Abstract: A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.

公开(公告)号：US20210104288A1

公开(公告)日：2021-04-08

申请号：US17101132

申请日：2020-11-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adolf Baumann ,  Mark Jung

IPC: G11C29/36 ,  G11C14/00

Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

公开(公告)号：US11914545B2

公开(公告)日：2024-02-27

申请号：US17564487

申请日：2021-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Andreas Waechter ,  Mark Jung ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F13/42 ,  G06F13/28 ,  H04L67/303

CPC classification number: G06F13/4234 ,  G06F13/28 ,  H04L67/303

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

公开(公告)号：US20230207036A1

公开(公告)日：2023-06-29

申请号：US18179434

申请日：2023-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adolf Baumann ,  Mark Jung

IPC: G11C29/36 ,  G11C14/00

CPC classification number: G11C29/36 ,  G11C14/0063 ,  G11C5/148 ,  G11C2029/3602

Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

公开(公告)号：US11600351B2

公开(公告)日：2023-03-07

申请号：US17101132

申请日：2020-11-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adolf Baumann ,  Mark Jung

IPC: G11C29/36 ,  G11C14/00 ,  G11C5/14

Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

公开(公告)号：US11243903B2

公开(公告)日：2022-02-08

申请号：US16658928

申请日：2019-10-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Andreas Waechter ,  Mark Jung ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F13/42 ,  G06F13/28 ,  H04L29/08

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

公开(公告)号：US20170109054A1

公开(公告)日：2017-04-20

申请号：US14887885

申请日：2015-10-20

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

Inventor： Andreas Waechter ,  Mark Jung ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F3/06 ,  G06F13/28 ,  G06F13/42 ,  H04L29/08

CPC classification number: G06F13/4234 ,  G06F13/28 ,  H04L67/303

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

公开(公告)号：US09454437B2

公开(公告)日：2016-09-27

申请号：US14309362

申请日：2014-06-19

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

Inventor： Andreas Waechter ,  Mark Jung ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F11/00 ,  G06F11/14 ,  G06F9/44

CPC classification number: G06F11/1417 ,  G06F9/4401 ,  G06F9/4418 ,  G06F11/1469

Abstract: A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.

Abstract translation: 处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。 标准引导顺序用于恢复数据的第一部分。 数据的第二部分与标准引导序列并行地从NVL阵列恢复。 对数据的第二部分执行数据损坏检查。 如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。 如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。 处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。