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公开(公告)号：US20170098651A1
公开(公告)日：2017-04-06
申请号：US15381080
申请日：2016-12-15
Applicant: Guobiao ZHANG
Inventor： Guobiao ZHANG
IPC: H01L27/102 , G11C11/56 , H01L27/112 , H01L21/8229 , H01L21/822
CPC classification number: G11C5/02 , G11C8/06 , G11C11/56 , G11C17/00 , G11C17/06 , G11C17/16 , G11C17/18 , G11C2213/71 , H01L21/8221 , H01L21/8229 , H01L25/0657 , H01L27/1021 , H01L27/11206 , H01L27/1128 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06506 , H01L2225/06562 , H01L2225/06582 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: The present invention discloses an offset-printing method for a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package. The mask-patterns for different 3D-op dice are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different 3D-oP dice.
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公开(公告)号：US09460811B2
公开(公告)日：2016-10-04
申请号：US14453779
申请日：2014-08-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
CPC classification number: G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
Abstract translation: 提供了具有冗余性和使用方法的只读存储器（ROM）。 具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。 一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。 字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。 提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。 提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。
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公开(公告)号：US09373410B1
公开(公告)日：2016-06-21
申请号：US14479111
申请日：2014-09-05
Applicant: Crossbar, Inc.
Inventor： Tanmay Kumar
CPC classification number: G11C17/146 , G11C11/5692 , G11C13/0004 , G11C13/0011 , G11C13/0069 , G11C17/00 , G11C17/18 , G11C2013/0073 , G11C2213/15 , G11C2213/33 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/148
Abstract: Providing for a memory cell capable of operating a one time programmable, multi-level cell memory is described herein. In some embodiments, a program signal having a first polarity and a first current compliance is applied to a memory cell. In an aspect, the memory cell is switched to a first program state from a non-program state in response to the first program signal. Furthermore, in an embodiment, an additional program signal having a second polarity is applied to the memory cell. In another aspect, the memory cell is switched to an additional program state different from the first program state in response to the additional program signal, wherein: the memory cell inherently resists switching back from the additional program state to the first program state, and the second polarity is opposite to the first polarity.
Abstract translation: 本文描述了提供能够操作一次可编程的多级单元存储器的存储单元。 在一些实施例中，具有第一极性和第一电流顺应性的程序信号被施加到存储器单元。 在一方面，响应于第一程序信号，存储器单元从非程序状态切换到第一编程状态。 此外，在一个实施例中，具有第二极性的附加节目信号被施加到存储单元。 在另一方面，响应于附加的程序信号，存储器单元被切换到与第一编程状态不同的附加程序状态，其中：存储单元固有地抵抗从附加程序状态切换到第一程序状态，并且 第二极性与第一极性相反。
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4.发明授权Method of starting camera in user equipment, user equipment and storage medium 有权在用户设备，用户设备和存储介质中启动摄像机的方法公开(公告)号：US09338446B2
公开(公告)日：2016-05-10
申请号：US14256583
申请日：2014-04-18
Inventor： Chao Gao , Xudong Qiu , Sanfeng Yan , Changsheng Zhou , Peng Jiang
CPC classification number: H04N17/002 , G11C17/00 , H04N5/23225 , H04N5/23229
Abstract: A method of starting a camera, a user equipment and a storage medium are provided. A memory in the user equipment is additionally utilized to store calibrated OTP data therein so that the calibrated OTP data stored in the memory can be written directly into a register of an optical sensor of the camera each time the user equipment accesses the camera to thereby avoid OTP data calibration each time the user equipment accesses the camera, and shorten a period of time for the user equipment to access the camera and a period of time for the camera to start while avoiding an overly amount of calibration calculations, lowering a load on a kernel of the user equipment and improving the experience of a user.
Abstract translation: 提供了一种启动相机，用户设备和存储介质的方法。 用户设备中的存储器还被用于在其中存储校准的OTP数据，使得存储在存储器中的校准OTP数据可以在每次用户设备访问相机时直接写入摄像机的光学传感器的寄存器，从而避免 OTP数据校准，每次用户设备访问摄像机，并缩短用户设备访问摄像机的时间段，并缩短相机启动的时间段，同时避免过多的校准计算，降低一个负载 内核的用户设备，提高用户体验。
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公开(公告)号：US09263149B2
公开(公告)日：2016-02-16
申请号：US13624255
申请日：2012-09-21
Applicant: SK hynix Inc.
Inventor： Tae Hoon Kim
Abstract: A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to the gate of the first MOS transistor, and a second switching device configured to provide a bias voltage at the other side of the source/drain of the first MOS transistor.
Abstract translation: 半导体器件包括一次性可编程（OTP）存储单元，其包括具有耦合到位线的栅极的第一MOS晶体管，耦合到第一MOS晶体管的源极/漏极的一侧的第一开关器件，被配置为 为提供给第一MOS晶体管的栅极的电流提供电流路径，以及被配置为在第一MOS晶体管的源极/漏极的另一侧提供偏置电压的第二开关器件。
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Patent Agency Ranking
公开(公告)号：US09123428B2
公开(公告)日：2015-09-01
申请号：US14318021
申请日：2014-06-27
Applicant: SK hynix Inc.
Inventor： Sungju Son , Youncheul Kim , Sungho Kim , Dongue Ko
CPC classification number: G11C17/18 , G11C17/00 , G11C17/16 , G11C17/165 , G11C29/027 , G11C29/787 , G11C2229/763 , H01L23/5256 , H01L2924/0002 , H01L2924/00
Abstract: An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.
Abstract translation: 电子熔丝阵列电路包括：垂直栅极类型的电子熔丝晶体管，其被配置为具有用于接收编程栅极线的电压并且在漏极端子和源极端子之间浮置的栅极的栅极; 以及掩埋栅极型选择晶体管，其配置为具有用于接收字线栅极线的电压的栅极，并且利用位线将漏极端子和源极端子之间的另一个电连接/断开。
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7.发明申请METHOD OF STARTING CAMERA IN USER EQUIPMENT, USER EQUIPMENT AND STORAGE MEDIUM 有权在用户设备，用户设备和存储介质中启动摄像机的方法公开(公告)号：US20150237342A1
公开(公告)日：2015-08-20
申请号：US14256583
申请日：2014-04-18
Inventor： Chao GAO , Xudong QIU , Sanfeng YAN , Changsheng ZHOU , Peng JIANG
CPC classification number: H04N17/002 , G11C17/00 , H04N5/23225 , H04N5/23229
Abstract: A method of starting a camera, a user equipment and a storage medium are provided. A memory in the user equipment is additionally utilized to store calibrated OTP data therein so that the calibrated OTP data stored in the memory can be written directly into a register of an optical sensor of the camera each time the user equipment accesses the camera to thereby avoid OTP data calibration each time the user equipment accesses the camera, and shorten a period of time for the user equipment to access the camera and a period of time for the camera to start while avoiding an overly amount of calibration calculations, lowering a load on a kernel of the user equipment and improving the experience of a user.
Abstract translation: 提供了一种启动相机，用户设备和存储介质的方法。 用户设备中的存储器还被用于在其中存储校准的OTP数据，使得存储在存储器中的校准OTP数据可以在每次用户设备访问相机时直接写入摄像机的光学传感器的寄存器，从而避免 OTP数据校准，每次用户设备访问摄像机，并缩短用户设备访问摄像机的时间段，并缩短相机启动的时间段，同时避免过多的校准计算，降低一个负载 内核的用户设备，提高用户体验。
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8.发明授权Low-pin-count non-volatile memory interface with soft programming capability 有权具有软编程能力的低引脚数非易失性存储器接口公开(公告)号：US09076513B2
公开(公告)日：2015-07-07
申请号：US14231404
申请日：2014-03-31
Applicant: Shine C. Chung
Inventor： Shine C. Chung
CPC classification number: G11C17/18 , G11C7/10 , G11C8/18 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/0408 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C17/00 , G11C17/146 , G11C17/16 , G11C29/022 , G11C29/027 , G11C29/1201 , G11C29/46 , G11C2216/30
Abstract: A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. At least one of the selected NVM cells can be coupled to at least one output register. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers controlled by the pulse of the first signal and voltage level and/or timing of the second signal. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines. Reading at least one of the NVM cells can be activated by a third signal or by detecting ramping of the first or the second supply voltage line.
Abstract translation: 具有不超过两个控制信号的低引脚数非易失性（NVM）存储器，可以至少编程NVM单元，将要编程的数据加载到输出寄存器中，或读取NVM单元。 至少一个NVM单元具有耦合到至少一个选择器和第一电源电压线的至少一个NVM元件。 选择器耦合到第二电源电压线并且具有选择信号。 所选择的NVM单元中的至少一个可以耦合到至少一个输出寄存器。 可以使用不超过两个控制信号来选择NVM中的至少一个NVM单元以将数据编程到至少一个NVM单元中，或者将数据加载到由第一信号的脉冲控制的至少一个输出寄存器中 和第二信号的电压电平和/或定时。 可以通过第一至第二电源电压线的电压电平来确定对NVM单元的编程或将数据加载到输出寄存器中。 读取至少一个NVM单元可以被第三信号激活或通过检测第一或第二电源电压线的斜坡。
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公开(公告)号：US08839054B2
公开(公告)日：2014-09-16
申请号：US13445187
申请日：2012-04-12
Applicant: George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
Inventor： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC: G11C29/00
CPC classification number: G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
Abstract translation: 提供了具有冗余性和使用方法的只读存储器（ROM）。 具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。 一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。 字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。 提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。 提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。
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公开(公告)号：US20140177364A1
公开(公告)日：2014-06-26
申请号：US13844937
申请日：2013-03-16
Applicant: SK HYNIX INC.
Inventor： Hyun-Su YOON
IPC: G11C29/00
Abstract: A one-time programmable memory device may include a normal cell array including a plurality of one-time programmable memory cells, which are programmable and accessible in the normal operation, a test cell array including one-time programmable memory cells, which are programmed at a given pattern in a test operation for determining a failed row and/or a failed column and are not accessible in the normal operation, a row circuit configured to control an operation of a row that is selected by a row address in the normal cell array, and a column circuit configured to access a column that is selected by a column address in the normal cell array.
Abstract translation: 一次性可编程存储器件可以包括正常单元阵列，其包括在正常操作中可编程和可访问的多个一次可编程存储器单元，包括一次可编程存储器单元的测试单元阵列，其被编程在 在用于确定故障行和/或故障列的测试操作中的给定模式，并且在正常操作中不可访问，行电路被配置为控制由正常单元阵列中的行地址选择的行的操作 以及被配置为访问由正常单元阵列中的列地址选择的列的列电路。
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