公开(公告)号：US09235487B2

公开(公告)日：2016-01-12

申请号：US14509820

申请日：2014-10-08

Applicant: SK hynix Inc.

Inventor： Jeongsu Jeong ,  Youncheul Kim ,  Hyunsu Yoon ,  Yonggu Kang ,  Kwidong Kim ,  Jeongtae Hwang

IPC: G11C7/00 ,  G06F11/20 ,  G11C7/20 ,  G11C29/44 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F2201/85 ,  G11C7/20 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402

Abstract: A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.

Abstract translation: 存储装置包括启动控制单元，其被配置为通过在初始化信号被激活时启动启动操作来控制启动操作的开始，并且在完成信号被激活之后忽略初始化信号，非易失性存储器单元 被配置为存储修复数据，并且在引导操作期间输出所存储的修复数据;多个寄存器，被配置为存储从非易失性存储器单元输出的修复数据;多个存储器组，被配置为用冗余代替正常单元 使用存储在多个电阻器中的相应寄存器中的修复数据的单元，以及被配置为生成完成信号以通知启动操作完成的验证单元。

公开(公告)号：US08879298B2

公开(公告)日：2014-11-04

申请号：US13672299

申请日：2012-11-08

Applicant: SK hynix Inc.

Inventor： Igsoo Kwon ,  Yeonuk Kim ,  Youncheul Kim

IPC: G11C17/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: An e-fuse array circuit includes a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage, a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage, a program/read line supplied with the high voltage when a program operation is activated, a read voltage, which is lower than the high voltage, when a read operation is activated, or the negative voltage when deactivated, a row line supplied with the ground voltage when the row line is activated or the negative voltage when the row line is deactivated, an e-fuse device supplied with voltage of the program/read line, a switch device controlled by the row line and configured to electrically connect the e-fuse device with a column line, and a column circuit configured to supply the negative voltage to the column line when the column line is activated.

Abstract translation: 电子熔丝阵列电路包括被配置为通过泵浦电源电压产生高电压的高电压抽运单元，被配置为通过泵送接地电压产生负电压的负电压抽运单元，提供有电源电压的程序/读取线 当激活读取操作时，当程序操作被激活时的高电压，低于高电压的读取电压，当被禁用时为负电压，当行线被激活时提供接地电压的行线，或者 当行线被去激活时的负电压，被提供有程序/读取线的电压的电熔丝装置，由行线控制并被配置为将电熔丝装置与列线电连接的开关装置，以及 列电路被配置为当列线被激活时将负电压提供给列线。

公开(公告)号：US09123428B2

公开(公告)日：2015-09-01

申请号：US14318021

申请日：2014-06-27

Applicant: SK hynix Inc.

Inventor： Sungju Son ,  Youncheul Kim ,  Sungho Kim ,  Dongue Ko

IPC: G11C5/02 ,  G11C5/06 ,  G11C17/18 ,  H01L23/525 ,  G11C17/16 ,  G11C17/00 ,  G11C29/02 ,  G11C29/00

CPC classification number: G11C17/18 ,  G11C17/00 ,  G11C17/16 ,  G11C17/165 ,  G11C29/027 ,  G11C29/787 ,  G11C2229/763 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.

Abstract translation: 电子熔丝阵列电路包括：垂直栅极类型的电子熔丝晶体管，其被配置为具有用于接收编程栅极线的电压并且在漏极端子和源极端子之间浮置的栅极的栅极; 以及掩埋栅极型选择晶体管，其配置为具有用于接收字线栅极线的电压的栅极，并且利用位线将漏极端子和源极端子之间的另一个电连接/断开。

公开(公告)号：US08817519B2

公开(公告)日：2014-08-26

申请号：US13672408

申请日：2012-11-08

Applicant: SK hynix Inc.

Inventor： Jeongsu Jeong ,  Youncheul Kim ,  Hyunsu Yoon ,  Yonggu Kang ,  Igsoo Kwon ,  Yeonuk Kim

IPC: G11C17/12 ,  G11C17/16 ,  G11C8/08 ,  G11C5/14

CPC classification number: G11C17/16 ,  G11C5/148 ,  G11C8/08 ,  G11C17/18

Abstract: An integrated circuit includes a high voltage generator generating a high voltage, a negative voltage generator generating a negative voltage, a divided voltage generator generating a divided voltage by dividing the power source voltage and supplying it to a read voltage terminal, a first power gate supplying the high voltage or the divided voltage to a program voltage terminal, a second power gate supplying the negative voltage or the ground voltage to a deactivation voltage terminal, a third power gate supplying the ground voltage or the divided voltage to an activation voltage terminal, and an e-fuse array circuit operating using voltage of the program voltage terminal as a program voltage, voltage of the divided voltage terminal as a read voltage, voltage of the activation voltage terminal as an activation voltage, and voltage of the deactivation voltage terminal as a deactivation voltage.

Abstract translation: 集成电路包括产生高电压的高压发生器，产生负电压的负电压发生器，分压电压发生器，通过分压电源电压产生分压，并将其提供给读电压端;第一供电电源 向编程电压端子施加高电压或分压，向停用电压端子提供负电压或接地电压的第二电源栅极，将接地电压或分压电压提供给激活电压端子的第三电源栅极，以及 使用编程电压端子的电压作为编程电压工作的电熔丝阵列电路，作为读取电压的分压电压端子的电压，作为激活电压的激活电压端子的电压，以及去激活电压端子的电压为 去激活电压。

公开(公告)号：US08885424B2

公开(公告)日：2014-11-11

申请号：US13672140

申请日：2012-11-08

Applicant: SK Hynix Inc.

Inventor： Jeongsu Jeong ,  Youncheul Kim ,  Hyunsu Yoon ,  Yonggu Kang ,  Kwidong Kim ,  Jeongtae Hwang

IPC: G11C7/10

CPC classification number: G06F11/2094 ,  G06F2201/85 ,  G11C7/20 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402

Abstract: A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.

Abstract translation: 存储装置包括启动控制单元，其被配置为通过在初始化信号被激活时启动启动操作来控制启动操作的开始，并且在完成信号被激活之后忽略初始化信号，非易失性存储器单元 被配置为存储修复数据，并且在引导操作期间输出所存储的修复数据;多个寄存器，被配置为存储从非易失性存储器单元输出的修复数据;多个存储器组，被配置为用冗余代替正常单元 使用存储在多个电阻器中的相应寄存器中的修复数据的单元，以及被配置为生成完成信号以通知启动操作完成的验证单元。

公开(公告)号：US08867288B2

公开(公告)日：2014-10-21

申请号：US13672528

申请日：2012-11-08

Applicant: SK Hynix Inc.

Inventor： Hyunsu Yoon ,  Jeongsu Jeong ,  Youncheul Kim ,  Gwangyeong Stanley Jeong ,  Hyunju Yoon

IPC: G11C29/44

CPC classification number: G11C29/4401 ,  G11C29/40 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/4002 ,  G11C2029/4402

Abstract: A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and programming the bank address and the row address to a nonvolatile memory when the data read from the multiple memory banks are different from each other.

Abstract translation: 用于测试存储器件的方法包括进入其中多个存储体以相同方式操作的测试模式，允许与多个存储体中的行地址相对应的行被激活，锁存存储体地址以及对应于 多个存储体，在由多个存储体中的列地址选择的列中写入相同的数据，读取从多个存储体写入数据中写入的数据，检查从多个存储体中的多个存储体读取的数据 当从多个存储体读取的数据彼此不同时，数据的读取彼此相等，并且将存储体地址和行地址编程到非易失性存储器。