公开(公告)号：US11907409B2

公开(公告)日：2024-02-20

申请号：US17488613

申请日：2021-09-29

申请人： Dell Products L.P.

发明人： Akkiah Choudary Maddukuri ,  Marshal Frederick Savage ,  Eugene David Cho ,  Sreeram Veluthakkal ,  Timothy M. Lambert

IPC分类号： G06F21/73 ,  G11C17/12 ,  G11C17/16 ,  G06F21/79

CPC分类号： G06F21/73 ,  G06F21/79 ,  G11C17/12 ,  G11C17/16

摘要： A method for dynamic immutable security personalization for enterprise products. Specifically, the disclosed method describes how a computer processor (e.g., baseboard management controller) of an enterprise product can personalize security requirements in trusted facilities, along the supply chain route of the enterprise product, so that trusted assumptions concerning the enterprise product can be made. Further, through dynamic immutable security personalization, these trusted assumptions are allowed to change over time (e.g., from being less restrictive to more restrictive) as changing enterprise product configuration states are captured while the enterprise product traverses the supply chain route.

公开(公告)号：US11856761B2

公开(公告)日：2023-12-26

申请号：US17477196

申请日：2021-09-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Sheng Chang ,  Chia-En Huang ,  Chun Chung Su ,  Wen-Hsing Hsieh

IPC分类号： H10B20/20 ,  H01L29/41 ,  G11C11/402 ,  G11C17/12 ,  G11C17/16 ,  H10B20/00 ,  H10B20/25 ,  H01L23/00

CPC分类号： H10B20/20 ,  G11C11/4023 ,  G11C17/12 ,  G11C17/123 ,  G11C17/16 ,  G11C17/165 ,  H01L29/413 ,  H10B20/25 ,  H10B20/30 ,  H10B20/367 ,  H10B20/60 ,  H01L23/573

摘要： A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

公开(公告)号：US11837299B2

公开(公告)日：2023-12-05

申请号：US17716122

申请日：2022-04-08

申请人： Chen-Feng Chang

发明人： Chen-Feng Chang ,  Tien-Sheng Chao

IPC分类号： G11C16/04 ,  G11C17/12 ,  G11C11/56 ,  H10B20/20 ,  H10B43/00

CPC分类号： G11C17/12 ,  G11C11/5671 ,  G11C16/0466 ,  H10B20/20 ,  H10B43/00

摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode, a first oxide located between the first electrode and the conductive gate, and a second oxide located between the second electrode and the conductive gate. The present invention creates an initial state wherein the transistor structure is not conducting, an intermediate state wherein the first oxide is punched through by the first voltage, and a fully opened state wherein both the first oxide and the second oxide are punched through. The aforementioned states allow storage of multiple bits on the read only memory.

公开(公告)号：US11676675B2

公开(公告)日：2023-06-13

申请号：US17848487

申请日：2022-06-24

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Ayaskanta Behera

IPC分类号： G11C17/12 ,  H01L27/112

CPC分类号： G11C17/12 ,  H01L27/112

摘要： A device includes a programmable ROM circuit, an address circuit, and a processor. The programmable ROM circuit includes multiple physically contiguous pairs of bit-cells, each pair of bit-cells includes an active layer trace extending continuously across both of the bit-cells, each pair of bit-cells comprises a shared contact layer point when the pair of bit-cells is programmed to a value of one and no shared contact layer point when the pair of bit-cells is programmed to a value of zero. The address circuit is coupled to the programmable ROM circuit and configured to address only a first bit-cell of each pair of bit-cells. The processor is coupled to the address circuit and the programmable ROM circuit and configured to use the address circuit to read data from one or more pairs of bit-cells of the programmable ROM circuit.

公开(公告)号：US20220343986A1

公开(公告)日：2022-10-27

申请号：US17722534

申请日：2022-04-18

申请人： Chen-Feng CHANG

发明人： Chen-Feng CHANG ,  Tien-Sheng CHAO

IPC分类号： G11C17/12 ,  H01L27/11563 ,  H01L27/112 ,  G11C11/56 ,  G11C16/04

摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode. A multiplicity of M nanowire channels is mounted between the first electrode and the second electrode, and M is a positive integer greater than one. The present invention breaks multiple states of the multi-bits read only memory. The multiple states are programmable and include an ith state, and 1

公开(公告)号：US11250930B2

公开(公告)日：2022-02-15

申请号：US16709019

申请日：2019-12-10

申请人： STMicroelectronics SA ,  STMicroelectronics (Rousset) SAS

发明人： Stephane Denorme ,  Philippe Candelier ,  Joel Damiens ,  Fabrice Marinet

IPC分类号： G11C17/00 ,  G11C29/52 ,  G11C17/12

摘要： A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

公开(公告)号：US10580499B2

公开(公告)日：2020-03-03

申请号：US15710851

申请日：2017-09-21

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hsin-Pang Lu ,  Chi-Hsiu Hsu ,  Chung-Hao Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai

IPC分类号： G11C16/24 ,  G11C7/18 ,  H01L27/112 ,  H01L27/02 ,  G11C17/12 ,  G06F17/50 ,  G11C7/02

摘要： A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

公开(公告)号：US20200058328A1

公开(公告)日：2020-02-20

申请号：US16523953

申请日：2019-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Meng-Sheng CHANG ,  Min-Shin WU ,  Yao-Jen YANG

IPC分类号： G11C5/02 ,  G06F17/50 ,  G11C7/18 ,  G11C8/14 ,  G11C17/16 ,  G11C17/12

摘要： A memory circuit array includes a first read device and a first program device. The first read device is coupled to a first bit line. The first read device includes a first transistor coupled to a first word line, and a second transistor coupled to the first word line. The first program device is coupled to the first read device. The first program device includes a third transistor coupled to a second word line, and a fourth transistor coupled to the second word line.

公开(公告)号：US10381076B2

公开(公告)日：2019-08-13

申请号：US15865116

申请日：2018-01-08

申请人： ARM Ltd.

发明人： Azeez Jennudin Bhavnagarwala ,  Vikas Chandra ,  Brian Tracy Cline

IPC分类号： H03M1/00 ,  G11C13/00 ,  G11C11/38 ,  G11C17/12 ,  H03M1/78 ,  H03M1/80

摘要： A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

公开(公告)号：US20190237113A1

公开(公告)日：2019-08-01

申请号：US15994264

申请日：2018-05-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuoyuan HSU ,  Jacklyn CHANG

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C17/12 ,  G11C7/18

CPC分类号： G11C7/062 ,  G11C7/12 ,  G11C7/18 ,  G11C17/12

摘要： A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a BL which represents a complement of the BL. The ROM device precharges the BL and the BL to a first logical value. The ROM device activates the memory cell which discharges the BL when the memory cell is coupled to the BL or discharges the BL when the memory cell is coupled to the BL. The ROM device reads the first logical value as being stored within the memory cell when the BL is less than the BL. Otherwise, the ROM device reads the second logical value as being stored within the memory cell when the BL is greater than the BL.