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    INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
    1.
    发明公开
    INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240268107A1

    公开(公告)日：2024-08-08

    申请号：US18165296

    申请日：2023-02-06

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Yao-Jen YANG ,  Shao-Tung PENG ,  Chung-I HUANG

    IPC分类号： H10B20/25

    CPC分类号： H10B20/25

    摘要： An integrated circuit includes a first active region, a second active region, a first fuse and a dummy fuse. The first active region extends in a first direction, and is on a first level. The second active region extends in the first direction, is on the first level, and is separated from the first active region in a second direction different from the first direction. The first fuse extends in the first direction, is on a second level, overlaps the first active region and is electrically coupled to the first active region. The dummy fuse extends in the first direction, is on the second level, and is separated from the first fuse in the second direction. The dummy fuse overlaps the second active region, and is not electrically coupled to the second active region.

    METHODS OF MANUFACTURING FUSIBLE STRUCTURES
    4.
    发明申请
    METHODS OF MANUFACTURING FUSIBLE STRUCTURES 有权

    公开(公告)号：US20220384339A1

    公开(公告)日：2022-12-01

    申请号：US17885321

    申请日：2022-08-10

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Shao-Ting WU ,  Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Chung-I HUANG

    IPC分类号： H01L23/525 ,  H01L27/112

    摘要： A method (fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion; and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.

    SEMICONDUCTOR DEVICE HAVING FUSE ARRAY AND METHOD OF MAKING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE HAVING FUSE ARRAY AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20210082812A1

    公开(公告)日：2021-03-18

    申请号：US16573761

    申请日：2019-09-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Po-Hsiang HUANG ,  An-Jiao FU ,  Chih-Hao CHEN

    IPC分类号： H01L23/525 ,  H01L21/768 ,  H01L23/00

    摘要： A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.

    SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL STRUCTURE
    6.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL STRUCTURE 审中-公开

    公开(公告)号：US20200058660A1

    公开(公告)日：2020-02-20

    申请号：US16533359

    申请日：2019-08-06

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Meng-Sheng CHANG ,  Yao-Jen YANG

    IPC分类号： H01L27/112 ,  H01L23/528 ,  H01L23/525 ,  G11C17/18 ,  G06F17/50 ,  G11C17/16

    摘要： A structure includes a word line, a bit line, and an anti-fuse cell. The anti-fuse cell includes a reading device, a programming device, and a dummy device. The reading device includes a first gate coupled to the first word line, a first source/drain region coupled to the bit line, and a second source/drain region. The first source/drain region and the second source/drain region are on opposite sides of the first gate. The programming device includes a second gate, a third source/drain region coupled to the second source/drain region, and a fourth source/drain region. The third source/drain region and the fourth source/drain region are on opposite sides of the second gate. The dummy device includes a third gate, a fifth source/drain region coupled to the fourth source/drain region, and a sixth source/drain region. The fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate.

    INTEGRATED CIRCUIT LAYOUT AND METHOD
    7.
    发明公开
    INTEGRATED CIRCUIT LAYOUT AND METHOD 审中-公开

    公开(公告)号：US20230354591A1

    公开(公告)日：2023-11-02

    申请号：US18346700

    申请日：2023-07-03

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Chien-Ying CHEN ,  Chia-En HUANG ,  Yih WANG

    IPC分类号： H10B20/20 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H10B20/20 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/528

    摘要： A method of generating an IC layout diagram includes abutting first and second cells to define a first active region including first and second anti-fuse bits, abutting third and fourth cells to define a second active region including third and fourth anti-fuse bits, and defining a third active region including fifth and sixth anti-fuse bits adjacent to the first through fourth anti-fuse bits. The first cell includes first and second via regions overlapping first and second gate regions shared by respective structures and transistors of the first, third, and fifth anti-fuse bits, the fourth cell includes third and fourth via regions overlapping third and fourth gate regions shared by respective transistors and structures of the second, fourth, and sixth anti-fuse bits, the third cell includes fifth and sixth via regions overlapping the first gate region, and the second cell includes seventh and eighth via regions overlapping the fourth gate region.

    METHOD OF AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD OF AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220237358A1

    公开(公告)日：2022-07-28

    申请号：US17342295

    申请日：2021-06-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yao-Jen YANG ,  Meng-Sheng CHANG

    IPC分类号： G06F30/392 ,  H01L27/02 ,  H01L27/118 ,  H01L27/12

    摘要： A method includes receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and a first active region having a first width in the first direction. The second cell has the cell height, and a second active region having a second width in the first direction. The second width is different from the first width. The method further includes manufacturing a semiconductor device according to the design layout.