公开(公告)号：US11538547B2

公开(公告)日：2022-12-27

申请号：US17094218

申请日：2020-11-10

Applicant: SK hynix Inc.

Inventor： Jingjian Ren ,  Alexey Lisichenok ,  Jay Kim ,  Sungho Kim ,  Eric Wong ,  Sunmin Yun

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/42

Abstract: Embodiments provide a scheme for determining the order of read threshold voltages used in a read error recovery operation for a memory system. A controller performs one or more read operations on a memory device using one or more read voltages among a plurality of read voltages in a set order. The controller detects a successful read operation among the one or more read operations. The controller determines one or more credits for the one or more read voltages, respectively, in response to the detected successful read operation. The controller updates the set order based on the determined credits.

公开(公告)号：US09123428B2

公开(公告)日：2015-09-01

申请号：US14318021

申请日：2014-06-27

Applicant: SK hynix Inc.

Inventor： Sungju Son ,  Youncheul Kim ,  Sungho Kim ,  Dongue Ko

IPC: G11C5/02 ,  G11C5/06 ,  G11C17/18 ,  H01L23/525 ,  G11C17/16 ,  G11C17/00 ,  G11C29/02 ,  G11C29/00

CPC classification number: G11C17/18 ,  G11C17/00 ,  G11C17/16 ,  G11C17/165 ,  G11C29/027 ,  G11C29/787 ,  G11C2229/763 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.

Abstract translation: 电子熔丝阵列电路包括：垂直栅极类型的电子熔丝晶体管，其被配置为具有用于接收编程栅极线的电压并且在漏极端子和源极端子之间浮置的栅极的栅极; 以及掩埋栅极型选择晶体管，其配置为具有用于接收字线栅极线的电压的栅极，并且利用位线将漏极端子和源极端子之间的另一个电连接/断开。