公开(公告)号：US20230402117A1

公开(公告)日：2023-12-14

申请号：US18362952

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Chia-En HUANG ,  Yih WANG

IPC: G11C17/16 ,  G11C17/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C17/12

CPC classification number: G11C17/16 ,  G11C17/06 ,  G11C17/123 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A method of operating a memory circuit includes turning on a first programming device and turning on a first selection device thereby causing a first current to flow through a first fuse element. The first fuse element is coupled between the first selection device and the first programming device. The method further includes turning off a second programming device and turning off a second selection device, and blocking the first current from flowing through a second fuse element that is coupled between the second selection device and the first programming device.

公开(公告)号：US11842780B2

公开(公告)日：2023-12-12

申请号：US17439454

申请日：2020-01-31

Applicant: Sony Semiconductor Solutions Corporation

Inventor： Mikio Oka ,  Yasuo Kanda ,  Kenji Noguchi

IPC: G11C17/16 ,  G11C17/06 ,  G11C17/18

CPC classification number: G11C17/06 ,  G11C17/18

Abstract: A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.

公开(公告)号：US20180301380A1

公开(公告)日：2018-10-18

申请号：US15950169

申请日：2018-04-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L29/786 ,  H01L29/78 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/683 ,  G11C29/00 ,  G11C17/14 ,  G11C17/06 ,  G11C16/04 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/8221 ,  G11C5/025 ,  G11C5/063 ,  G11C8/10 ,  G11C13/003 ,  G11C16/0483 ,  G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  G11C29/021 ,  G11C29/028 ,  G11C29/82 ,  G11C2213/71 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8238 ,  H01L21/823871 ,  H01L21/823885 ,  H01L21/84 ,  H01L21/845 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11803 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/785 ,  H01L29/78696 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0016 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.

公开(公告)号：US20180218946A1

公开(公告)日：2018-08-02

申请号：US15904347

申请日：2018-02-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L21/822 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L29/786 ,  H01L29/78 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/683 ,  G11C29/00 ,  G11C17/14 ,  G11C17/06 ,  G11C16/04 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/8221 ,  G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  G11C17/06 ,  G11C17/14 ,  G11C29/82 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/845 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11803 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/785 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796

Abstract: A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.

公开(公告)号：US09767915B2

公开(公告)日：2017-09-19

申请号：US15297922

申请日：2016-10-19

Applicant: Attopsemi Technology Co., LTD

Inventor： Shine C. Chung

IPC: G11C17/16 ,  G11C17/06 ,  G11C13/00 ,  G11C7/22 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06 ,  G11C17/18 ,  H01L23/525 ,  H01L27/102 ,  H01L27/112 ,  G11C11/16 ,  G11C17/02 ,  H01L29/732

CPC classification number: G11C17/06 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0054 ,  G11C2213/72 ,  G11C2213/74 ,  H01L23/5256 ,  H01L27/1021 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/732 ,  H01L29/861 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof.

公开(公告)号：US20170098651A1

公开(公告)日：2017-04-06

申请号：US15381080

申请日：2016-12-15

Applicant: Guobiao ZHANG

Inventor： Guobiao ZHANG

IPC: H01L27/102 ,  G11C11/56 ,  H01L27/112 ,  H01L21/8229 ,  H01L21/822

CPC classification number: G11C5/02 ,  G11C8/06 ,  G11C11/56 ,  G11C17/00 ,  G11C17/06 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/71 ,  H01L21/8221 ,  H01L21/8229 ,  H01L25/0657 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/1128 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention discloses an offset-printing method for a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package. The mask-patterns for different 3D-op dice are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different 3D-oP dice.

公开(公告)号：US20160012907A1

公开(公告)日：2016-01-14

申请号：US14853488

申请日：2015-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongku KANG ,  Dae Yeal LEE

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/24 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C11/56 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3481 ,  G11C17/06

Abstract: A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.

Abstract translation: 提供一种包括包括多个存储单元的单元阵列的非易失性存储器件; 页面缓冲器单元，其包括多个页缓冲器，并且被配置为在程序验证操作时检测所选存储单元的编程是否完成; 以及控制逻辑，被配置为根据感测结果提供用于将每个页缓冲器的数据锁存器设置为编程禁止状态的设置脉冲，其中控制逻辑将设置脉冲提供给至少两个不同的页缓冲器，使得数据锁存 设置至少两个不同页面缓冲器。

公开(公告)号：US09165672B2

公开(公告)日：2015-10-20

申请号：US14077606

申请日：2013-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongku Kang ,  Dae Yeal Lee

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C17/06

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C11/56 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3481 ,  G11C17/06

Abstract: A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.

Abstract translation: 提供一种包括包括多个存储单元的单元阵列的非易失性存储器件; 页面缓冲器单元，其包括多个页缓冲器，并且被配置为在程序验证操作时检测所选存储单元的编程是否完成; 以及控制逻辑，被配置为根据感测结果提供用于将每个页缓冲器的数据锁存器设置为编程禁止状态的设置脉冲，其中控制逻辑将设置脉冲提供给至少两个不同的页缓冲器，使得数据锁存 设置至少两个不同页面缓冲器。

公开(公告)号：US09013918B2

公开(公告)日：2015-04-21

申请号：US13320331

申请日：2011-08-10

Applicant: Qingqing Liang ,  Xiaodong Tong ,  Huicai Zhong ,  Huilong Zhu

Inventor： Qingqing Liang ,  Xiaodong Tong ,  Huicai Zhong ,  Huilong Zhu

IPC: G11C11/39 ,  G11C17/06 ,  H01L27/102

CPC classification number: G11C11/39 ,  G11C17/06 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/1027

Abstract: A two-terminal memory cell includes a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the memory cell by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the memory cell by applying a reverse bias, which is approaching to the reverse breakdown region of the memory cell, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the memory cell may be effectively used for data storage.

Abstract translation: 双端存储单元包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。 可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来将第一数据状态存储在存储单元中。 可以通过在第一P型半导体层和第二N型半导体层之间施加接近存储单元的反向击穿区域的反向偏压来将第二数据状态存储在存储单元中。 以这种方式，存储单元可以有效地用于数据存储。

公开(公告)号：US08897056B2

公开(公告)日：2014-11-25

申请号：US13952990

申请日：2013-07-29

Applicant: SanDisk 3D LLC

Inventor： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

IPC: G11C11/36 ,  H01L27/102 ,  G11C17/16 ,  G11C13/00 ,  G11C11/56 ,  G11C17/14 ,  H01L27/10 ,  G11C17/06 ,  H01L45/00

CPC classification number: G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

Abstract: A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.

Abstract translation: 提供了一种柱状存储单元，其包括转向元件和与该转向元件串联联接的非易失性状态变化元件。 还提供其他方面。