公开(公告)号：US09607877B2

公开(公告)日：2017-03-28

申请号：US13376731

申请日：2011-03-04

Applicant: Huicai Zhong ,  Qingqing Liang

Inventor： Huicai Zhong ,  Qingqing Liang

IPC: H01L23/34 ,  H01L27/12 ,  H05K7/20 ,  H01L21/762 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L27/0694 ,  H01L27/088

Abstract: The present invention provides a substrate structure, a semiconductor device, and a manufacturing method thereof. The substrate structure comprises: a semiconductor substrate; and a first isolation region, wherein the first isolation region comprises: a first trench extending through the semiconductor substrate; and a first dielectric layer filling the first trench. Due to the isolation region extending through the substrate, it is possible to make device structures on both surfaces of the substrate, so as to increase the utilization of the substrate and the integration degree of the devices.

公开(公告)号：US09070719B2

公开(公告)日：2015-06-30

申请号：US13577942

申请日：2011-11-18

Applicant: Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

IPC: H01L21/762 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

Abstract translation: 公开了一种半导体器件结构，其制造方法和半导体鳍片的制造方法。 在一个实施例中，制造半导体器件结构的方法包括：在半导体衬底上沿第一方向形成翅片; 在第二方向上形成栅极线，在半导体衬底上与第一方向交叉的第二方向和与鳍状物交叉的栅极线与夹在栅极线和鳍之间的栅极电介质层形成栅极线; 形成围绕所述栅极线的介电隔离层; 以及在预定位置执行器件间电隔离，其中所述栅极线的隔离部分形成各个器件的独立栅电极。

公开(公告)号：US09048286B2

公开(公告)日：2015-06-02

申请号：US13159351

申请日：2011-06-13

Applicant: Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/7624 ,  H01L21/76283

Abstract: The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.

Abstract translation: 本发明涉及IC的基板及其制造方法。 该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

公开(公告)号：US09024435B2

公开(公告)日：2015-05-05

申请号：US13379347

申请日：2011-08-12

Applicant: Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Jiang Yan ,  Chao Zhao

IPC: H01L23/34 ,  H01L23/522 ,  H01L23/467 ,  H01L23/473

CPC classification number: H01L23/522 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating.

Abstract translation: 提供半导体器件，其形成方法和封装结构。 半导体器件包括：形成金属氧化物半导体场效应晶体管（MOSFET）的半导体衬底; 介电层，设置在所述半导体衬底上并覆盖所述MOSFET，其中在所述电介质层中形成多个互连结构; 以及嵌入在互连结构之间的电介质层中的至少一个散热路径，用于使液体或气体在散热路径中循环，其中散热路径的开口暴露在介电层的表面上。 本发明可以提高散热效率，防止芯片过热。

公开(公告)号：US08987136B2

公开(公告)日：2015-03-24

申请号：US13380061

申请日：2011-02-27

Applicant: Huicai Zhong ,  Qingqing Liang

Inventor： Huicai Zhong ,  Qingqing Liang

IPC: H01L21/44 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/76895 ,  H01L21/76897

Abstract: A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.

Abstract translation: 提供半导体器件和用于制造半导体器件的局部互连结构的方法。 该方法包括在半导体衬底上的栅极的两侧上的侧壁间隔件和外侧壁间隔件之间形成可移除的牺牲侧壁间隔件，以及在侧壁间隔件和外侧壁之间的局部互连结构中的源极/漏极区域处形成接触通孔 在去除牺牲侧壁间隔物之后立即在栅极的同一侧上间隔开。 一旦源极/漏极通孔填充有导电材料以形成接触孔，接触孔的高度应与栅极的高度相同。 在本地互连结构中，建立后续的第一金属布线层和源极/漏极区域或较低电平的栅极区域之间的电连接的接触通孔应制成相同的深度。

公开(公告)号：US08987127B2

公开(公告)日：2015-03-24

申请号：US14361944

申请日：2012-03-23

Applicant: Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

Inventor： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L21/28097 ,  H01L21/283 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.

Abstract translation: 本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。 根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域， 因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。

公开(公告)号：US08975700B2

公开(公告)日：2015-03-10

申请号：US13380806

申请日：2011-08-09

Applicant: Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

Inventor： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L29/7849 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203

Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.

Abstract translation: 本发明涉及半导体器件及其制造方法。 根据本发明实施例的半导体器件包括：基底，其包括基底层，基底层上的绝缘层和绝缘层上的半导体层; 以及形成在所述衬底上的第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管通过形成在所述衬底中的沟槽隔离结构彼此隔离。 其中在第一和第二晶体管中的至少一个晶体管下方的基底层的至少一部分被应变，并且基底层的应变部分与绝缘层相邻。 根据本发明的半导体器件增加了器件的速度，从而提高了器件的性能。

公开(公告)号：US08933504B2

公开(公告)日：2015-01-13

申请号：US13807010

申请日：2011-11-30

Applicant: Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

Inventor： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L29/7827 ,  H01L21/28008 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/78642

Abstract: The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.

Abstract translation: 本发明公开了一种半导体结构，包括：衬底，导体层和围绕衬底上的导体层的电介质层; 覆盖所述导体层和所述电介质层的第一绝缘层; 形成在第一绝缘层上的栅极导体层和围绕栅极导体层的电介质层; 以及覆盖所述栅极导体层和围绕所述栅极导体层的所述电介质层的第二绝缘层; 其中填充有半导体材料的通孔垂直地穿过栅极导体层，通孔的底部停在导体层上，并且用作漏极/源极的第一导体插塞设置在通孔的顶部 ; 和用作源/漏电极的第二导体插头与导体层电接触，并且用作栅电极的第三导体插头电接触栅极导体层。

公开(公告)号：US08759923B2

公开(公告)日：2014-06-24

申请号：US13131745

申请日：2011-02-25

Applicant: Huicai Zhong ,  Qingqing Liang

Inventor： Huicai Zhong ,  Qingqing Liang

IPC: H01L27/088

CPC classification number: H01L29/78 ,  H01L21/76229 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/7831

Abstract: The present invention provides a semiconductor device structure and a method for manufacturing the same. The method comprises: providing a semiconductor substrate, forming a first insulating layer on the surface of the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a stripe-type trench embedded in the first insulating layer and the semiconductor substrate; forming a channel region in the trench; forming a gate stack line on the channel region and source/drain regions on opposite sides of the channel region. Embodiments of the present invention are applicable to manufacture of semiconductor devices.

Abstract translation: 本发明提供一种半导体器件结构及其制造方法。 该方法包括：提供半导体衬底，在半导体衬底的表面上形成第一绝缘层; 形成嵌入在所述第一绝缘层和所述半导体衬底中的浅沟槽隔离体; 形成嵌入在所述第一绝缘层和所述半导体衬底中的条状沟槽; 在沟槽中形成沟道区; 在通道区域的相对侧上的沟道区域和源极/漏极区域上形成栅极堆叠线。 本发明的实施例可应用于半导体器件的制造。

公开(公告)号：US20140110756A1

公开(公告)日：2014-04-24

申请号：US13981808

申请日：2012-07-24

Applicant: Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong ,  Hao Wu

Inventor： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong ,  Hao Wu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L21/2815 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78639 ,  H01L29/78654

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.

Abstract translation: 公开了半导体装置及其制造方法。 在一个实施例中，该方法包括：在衬底上顺序形成牺牲层和半导体层; 在所述半导体层上形成第一覆盖层; 形成以第一覆盖层为掩模延伸到基板的开口; 通过所述开口选择性地去除所述牺牲层的至少一部分，并且由于去除所述牺牲层而在绝缘材料中填充绝缘材料; 在开口中形成源极和漏极区域之一; 在所述基板上形成第二覆盖层; 以第二覆盖层为掩模形成源区和漏区中的另一个; 去除所述第二覆盖层的一部分; 以及形成栅极电介质层，并且在所述第二覆盖层的剩余部分的侧壁上形成隔板形式的栅极导体。