公开(公告)号：US20120132923A1

公开(公告)日：2012-05-31

申请号：US13159351

申请日：2011-06-13

Applicant: Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/161 ,  H01L29/20 ,  H01L21/76

CPC classification number: H01L21/76232 ,  H01L21/7624 ,  H01L21/76283

Abstract: The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.

Abstract translation: 本发明涉及IC的基板及其制造方法。 该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

公开(公告)号：US09048286B2

公开(公告)日：2015-06-02

申请号：US13159351

申请日：2011-06-13

Applicant: Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huicai Zhong ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/7624 ,  H01L21/76283

Abstract: The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.

Abstract translation: 本发明涉及IC的基板及其制造方法。 该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

公开(公告)号：US20130200456A1

公开(公告)日：2013-08-08

申请号：US13696995

申请日：2011-11-29

Applicant: Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L27/12 ,  H01L21/743 ,  H01L21/762 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.

Abstract translation: 本发明涉及半导体衬底，具有半导体衬底的集成电路及其制造方法。 根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括：半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层，其中，在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔，以穿透所述第二绝缘材料层，以将所述第一导电材料层与 第二导电材料层，每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。

公开(公告)号：US08957481B2

公开(公告)日：2015-02-17

申请号：US13379407

申请日：2011-05-11

Applicant: Huilong Zhu ,  Huicai Zhong ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Huicai Zhong ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L21/70 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/308 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost. By forming the contacts self-aligned with the gate, the method avoids misalignment and improves performance of the device while reducing a footprint of the device and lowering manufacture cost of the device.

Abstract translation: 本申请公开了一种半导体结构及其制造方法。 与传统的形成触点的方法相比，本公开减少了接触电阻，并且避免了栅极和接触插塞之间的短路，同时简化了制造工艺，增加了集成密度并降低了制造成本。 根据本公开的制造方法，形成第二浅沟槽隔离件，其上表面高于源极/漏极区域的上表面。 由栅极的侧壁间隔物，第二浅沟槽隔离件的侧壁间隔件和源极/漏极区域的上表面限定的区域形成为接触孔。 通过用导电材料填充接触孔来形成触点。 该方法省略了用于提供接触孔的蚀刻步骤，这降低了制造成本。 通过形成与栅极自对准的触点，该方法避免了未对准并且提高了器件的性能，同时减少了器件的占地面积并降低了器件的制造成本。

公开(公告)号：US08829621B2

公开(公告)日：2014-09-09

申请号：US13696995

申请日：2011-11-29

Applicant: Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

IPC: H01L21/70 ,  H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L21/74 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L27/12 ,  H01L21/743 ,  H01L21/762 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.

Abstract translation: 本发明涉及半导体衬底，具有半导体衬底的集成电路及其制造方法。 根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括：半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层，其中，在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔，以穿透所述第二绝缘材料层，以将所述第一导电材料层与 第二导电材料层，每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。

公开(公告)号：US08633522B2

公开(公告)日：2014-01-21

申请号：US13062733

申请日：2010-09-20

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Huicai Zhong

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Huicai Zhong

IPC: H01L29/78

CPC classification number: H01L29/7834 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.

Abstract translation: 半导体结构及其制造方法。 半导体结构包括半导体衬底; 形成在所述半导体衬底中的沟道区; 包括电介质层和导电层并形成在沟道区上方的栅极; 源极和漏极区域形成在栅极的相对侧; 第一浅沟槽隔离物嵌入半导体衬底并具有平行于栅极长度方向的长度方向; 以及第二浅沟槽隔离件，每个隔离件邻接源极或漏极区域的外侧壁并邻接第一浅沟槽隔离物，其中源极和漏极区域包括邻接第二浅沟槽隔离物的第一晶种层和顶部 第二浅沟槽隔离物的表面高于或高于源区和漏区的顶表面。

公开(公告)号：US20120273901A1

公开(公告)日：2012-11-01

申请号：US13063733

申请日：2010-09-27

Applicant: Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/49 ,  H01L29/66583 ,  H01L29/7833

Abstract: The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, when a gate is formed via a replacement gate process, a portion of a work function metal layer and a portion of a first metal layer are removed after the work function metal layer and the first metal layer are formed, and then the removed portions are replaced with a second metal layer. A device having such a gate structure greatly reduces the resistivity of the whole gate, due to a portion of the work function metal layer with a high resistivity being removed and the removed portion being filled with the second metal layer with a low resistivity, thereby AC performances of the device are improved.

Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 根据本发明，当通过替换栅极工艺形成栅极时，在形成功函数金属层和第一金属层之后，去除功函数金属层的一部分和第一金属层的一部分，以及 然后用第二金属层代替去除的部分。 具有这种栅极结构的器件大大降低了整个栅极的电阻率，这是由于去除具有高电阻率的功函数金属层的一部分并且被去除的部分被低电阻率的第二金属层填充，由此AC 改善了设备的性能。

公开(公告)号：US20120168881A1

公开(公告)日：2012-07-05

申请号：US13142591

申请日：2011-01-27

Applicant: Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Abstract translation: 本发明提供一种半导体器件及其制造方法。 制造半导体器件的方法包括：提供其上形成有栅极叠层结构并具有{100}晶体指数的硅衬底; 形成层叠所述硅衬底的顶表面的层间电介质层; 在所述层间介质层和/或所述栅堆叠结构中形成第一沟槽，所述第一沟槽具有沿着晶体方向并且垂直于所述栅堆叠结构的延伸方向; 以及用第一介电层填充所述第一沟槽，其中所述第一介电层是拉伸应力介电层。 本发明通过使用简单的工艺在沟道区域的横向上引入拉伸应力，这提高了半导体器件的响应速度和性能。

公开(公告)号：US20120049249A1

公开(公告)日：2012-03-01

申请号：US13062733

申请日：2010-09-20

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Huicai Zhong

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Huicai Zhong

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7834 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.

Abstract translation: 半导体结构及其制造方法。 半导体结构包括半导体衬底; 形成在所述半导体衬底中的沟道区; 包括电介质层和导电层并形成在沟道区上方的栅极; 源极和漏极区域形成在栅极的相对侧; 第一浅沟槽隔离物嵌入半导体衬底并具有平行于栅极长度方向的长度方向; 以及第二浅沟槽隔离件，每个隔离件邻接源极或漏极区域的外侧壁并邻接第一浅沟槽隔离物，其中源极和漏极区域包括邻接第二浅沟槽隔离物的第一晶种层和顶部 第二浅沟槽隔离物的表面高于或高于源区和漏区的顶表面。

公开(公告)号：US08716095B2

公开(公告)日：2014-05-06

申请号：US12997625

申请日：2010-09-19

Applicant: Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

Inventor： Huicai Zhong ,  Zhijiong Luo ,  Qingqing Liang

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28176 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.

Abstract translation: 具有牺牲氧清除金属间隔物的栅极堆叠的制造方法包括：在半导体衬底上形成由界面氧化物层，高K电介质层和金属栅电极组成的栅叠层结构; 保形地沉积覆盖半导体衬底和栅极堆叠结构的金属层; 并且选择性地蚀刻金属层以去除覆盖栅极堆叠结构和半导体衬底的顶表面的金属层的部分，以便仅将围绕栅极堆叠结构的牺牲氧清除金属间隔物保持在外部周边 门堆栈结构。 通过该方法制造的半导体器件。