Invention Grant
US08829621B2 Semiconductor substrate for manufacturing transistors having back-gates thereon
有权
用于制造其上具有背栅的晶体管的半导体衬底
- Patent Title: Semiconductor substrate for manufacturing transistors having back-gates thereon
- Patent Title (中): 用于制造其上具有背栅的晶体管的半导体衬底
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Application No.: US13696995Application Date: 2011-11-29
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Publication No.: US08829621B2Publication Date: 2014-09-09
- Inventor: Huilong Zhu , Zhijiong Luo , Haizhou Yin , Huicai Zhong
- Applicant: Huilong Zhu , Zhijiong Luo , Haizhou Yin , Huicai Zhong
- Applicant Address: CN Beijing
- Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee Address: CN Beijing
- Agency: Martine Penilla Group, LLP
- Priority: CN201110263458 20110907
- International Application: PCT/CN2011/001993 WO 20111129
- International Announcement: WO2013/033876 WO 20130314
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L27/12 ; H01L21/84 ; H01L27/092 ; H01L21/74 ; H01L21/762 ; H01L29/786

Abstract:
The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.
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