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公开(公告)号：US12237213B2
公开(公告)日：2025-02-25
申请号：US17631932
申请日：2021-11-12
Inventor： Libin Zhang , Yayi Wei , Zhen Song
IPC: H01L21/768 , H01L29/40 , G03F7/09
Abstract: A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1. The photolithographic coating is exposed to a light having a first wavelength, to image the to-be-connected structure to a first region of the photolithographic film. The photolithographic coating is exposed to a light having a second wavelength through a mask, to image the mask to a second region of the photolithographic film. A region in which the first region and the second region overlap serves as a connection region corresponding to the to-be-connected structure, and thereby self-alignment between a layer of the to-be-connected structure and a layer where a contact hole is arranged is implemented.
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公开(公告)号：US20250031379A1
公开(公告)日：2025-01-23
申请号：US18397387
申请日：2023-12-27
Abstract: The present disclosure provides a semiconductor device based on a dielectric material containing a metal interstitial impurity, including: a substrate, a dielectric material layer, and a functional layer. A material for preparing the dielectric material layer is a compound containing the metal interstitial impurity. The dielectric material layer and/or the functional layer is configured to subject to at least one of electricity, heat, light or magnetism, such that the dielectric material layer reaches a crystallization temperature to transit from a first state to a second state.
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公开(公告)号：US12205623B2
公开(公告)日：2025-01-21
申请号：US18004968
申请日：2020-07-20
Abstract: Provided is a cache memory, including: a first field-effect transistor, a field-like spin torque layer underneath a magnetic tunnel junction, an electrode, and a second field-effect transistor sequentially arranged and connected; wherein the first field-effect transistor is configured to provide a writing current and to control the on-off of the writing current through a gate electrode; the field-like spin torque layer is configured to generate field-like spin torques for switching a first ferromagnetic layer of the magnetic tunnel junction; the magnetic tunnel junction includes a first ferromagnetic layer, a tunneling layer, a second ferromagnetic layer and a pinning layer arranged sequentially; the electrode is configured to connect the cache memory with the second field-effect transistor; and the second field-effect transistor is configured to control the on-off of the second field-effect transistor through the gate electrode to read the resistive state of the magnetic tunnel junction.
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公开(公告)号：US20250015084A1
公开(公告)日：2025-01-09
申请号：US18763440
申请日：2024-07-03
Inventor： Yongliang Li , Fei Zhao
IPC: H01L27/092 , H01L21/225 , H01L21/762 , H01L29/06 , H01L29/161 , H01L29/24 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A semiconductor device and a method for manufacturing the same. The semiconductor device comprises an n-channel GAA transistor and a p-channel GAA transistor, which are spaced apart. Each of the n-channel GAA transistor and the p-channel GAA transistor comprises a source, a drain, and at least one nanostructure layer located between the source and the drain. The p-channel GAA transistor further comprises a gate stack structure and a gate sidewall. In the p-channel GAA transistor, the at least one nanostructure layer comprises a channel portion that is covered by the gate stack structure and a connecting portion that is covered by the gate sidewall, and germanium content in the channel portion is greater than germanium content in the connecting portion and is greater than germanium content in the at least one nanostructure layer of the n-channel GAA transistor.
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公开(公告)号：US20250006813A1
公开(公告)日：2025-01-02
申请号：US18754572
申请日：2024-06-26
Inventor： Yongliang LI , Fei ZHAO
IPC: H01L29/423 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A transistor and a manufacturing method. The transistor includes a semiconductor base substrate, an active structure, a dielectric structure, and a gate stack structure. The active structure is formed on the semiconductor base substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least two nanostructures stacked in a thickness direction of the semiconductor base substrate. In the channel region, a bottom nanostructure has a greater width than other nanostructures. The dielectric structure is formed between the semiconductor base substrate and the active structure. The dielectric structure is in contact with the bottom nanostructure. The gate stack structure is formed on a surface of the bottom nanostructure not in contact with the dielectric structure, and the gate stack surrounds a periphery of the other nanostructures.
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Patent Agency Ranking
公开(公告)号：US20250006556A1
公开(公告)日：2025-01-02
申请号：US18618706
申请日：2024-03-27
Inventor： Xianyu CHEN , Huilong ZHU
IPC: H01L21/768
Abstract: Provided are a self-aligned nanometer through-silicon-via structure and a method of preparing the same. According to the preset range and positions of the first and second trenches, the second preset pattern is formed, and then the first initial blind hole is formed by etching based on the second preset pattern, so that the position of the nanometer through-silicon-via is determined. The depth of the buried power rail may be determined by etching the silicon substrate with the first preset depth, and the depth of the self-aligned nanometer through-silicon-via may be determined by etching the silicon substrate with the second preset depth or thinning the fourth structure from a side of the silicon substrate.
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公开(公告)号：US20240372009A1
公开(公告)日：2024-11-07
申请号：US18565701
申请日：2021-11-26
Inventor： Huilong ZHU
IPC: H01L29/786 , H01L21/225 , H01L21/784 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/775
Abstract: A semiconductor device having a double-gate structure and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a first gate stack and a second gate stack on opposite sides of the channel portion in a first direction lateral to the substrate. A distance between an upper edge and/or a lower edge of an end of the first gate stack facing the channel portion in a vertical direction and a corresponding source/drain portion may be less than a distance between a corresponding upper edge and/or a corresponding lower edge of an end of the second gate stack facing the channel portion in the vertical direction and a corresponding source/drain portion.
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8.发明公开公开(公告)号：US20240345488A1
公开(公告)日：2024-10-17
申请号：US18294989
申请日：2021-12-29
Inventor： Dandan Han , Yayi Wei
IPC: G03F7/00
CPC classification number: G03F7/70516 , G03F7/70141 , G03F7/70258 , G03F7/70558
Abstract: A method for fast precise optical calibration on a photolithography system, including: determining a fitting relationship for a spot width corresponding to a point light source based on distribution of field strength generated by the point light source at an exit plane of a focusing element; determining, based on the fitting relationship, a first correspondence between the spot width and a parameter for exposing a photoresist, where the spot width in the first correspondence is for optical microscopy; determining a first spot-width dataset for the point light source based on an optical microscopic image of a spot-mapping pattern on a surface of the photoresist; determining, based on the first spot-width dataset, a second correspondence between the spot width and the parameter; and determining the first correspondence as a means for determining the parameter, when the first correspondence and the second correspondence meet a preset condition.
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公开(公告)号：US20240334838A1
公开(公告)日：2024-10-03
申请号：US18293846
申请日：2022-03-02
Inventor： Guozhong Xing , Long Liu , Xuefeng Zhao , Di Wang , Huai Lin , Hao Zhang , Ziwei Wang
CPC classification number: H10N50/10 , G11C5/063 , G11C11/161 , G11C11/1673 , G11C11/1675 , H10B61/20 , H10N50/20 , H10N50/85 , H10N52/101
Abstract: The present disclosure provides an SOT-MRAM memory cell, including: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor, a drain of which is connected to the orbital Hall effect layer; and a second transistor, a drain of which is connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.
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公开(公告)号：US20240305297A1
公开(公告)日：2024-09-12
申请号：US18258706
申请日：2020-12-25
Inventor： Zhi LI , Jianzhong ZHAO , Yumei ZHOU
IPC: H03K19/0175
CPC classification number: H03K19/0175
Abstract: Provided is a signal driving system with a constant slew. The signal driving system with the constant slew includes: a step voltage generation unit configured to provide multiplex arithmetic gradient voltage signals; a multiplexer, wherein an input end of the multiplexer is connected to the step voltage generation unit to receive the multiplex arithmetic gradient voltage signals, and another input end of the multiplexer is connected to a control signal generation unit, and the multiplexer is configured to selectively output the multiplex arithmetic gradient voltage signals under a control of a control signal generated by the control signal generation unit; a voltage following unit connected to the multiplexer, wherein the voltage following unit is configured to serve as an isolation and improve a driving ability; and an output following unit connected to the voltage following unit, wherein the output following unit is configured to drive a subsequently-connected load unit.
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