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    Method of fabricating thin film transistor
    6.
    发明授权
    Method of fabricating thin film transistor 有权
    制造薄膜晶体管的方法

    公开(公告)号：US08652885B2

    公开(公告)日：2014-02-18

    申请号：US11760869

    申请日：2007-06-11

    申请人： Byoung-Deog Choi ,  Sung-Sik Bae ,  Won-Sik Kim

    发明人： Byoung-Deog Choi ,  Sung-Sik Bae ,  Won-Sik Kim

    IPC分类号： H01L21/00

    CPC分类号： H01L27/12 ,  H01L29/78615 ,  H01L29/78639 ,  H01L29/78675

    摘要： A method of fabricating a thin film transistor includes forming an active layer on an insulating substrate; forming a gate insulation film on the insulating substrate; forming source, drain, and body contact regions which are separated by a channel region in the active layer; forming a gate on the gate insulation film; forming an interlayer insulation film on the insulating substrate; and forming source and drain electrodes electrically connected with the source and drain regions, respectively, wherein a voltage is applied to the channel region of the active layer through the body contact region, and the body contact region is connected to the source or drain electrode.

    摘要翻译： 制造薄膜晶体管的方法包括在绝缘基板上形成有源层; 在绝缘基板上形成栅极绝缘膜; 形成由有源层中的沟道区分隔的源极，漏极和体接触区域; 在栅极绝缘膜上形成栅极; 在绝缘基板上形成层间绝缘膜; 以及分别形成与源极和漏极区域电连接的源极和漏极，其中电压通过本体接触区域施加到有源层的沟道区域，并且主体接触区域连接到源极或漏极电极。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
    7.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 有权
    形成半导体结构的方法

    公开(公告)号：US20120126289A1

    公开(公告)日：2012-05-24

    申请号：US13359174

    申请日：2012-01-26

    申请人： Terry Sparks

    发明人： Terry Sparks

    IPC分类号： H01L29/78

    CPC分类号： H01L29/78639 ,  H01L21/32135 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78654

    摘要： A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium.

    摘要翻译： 形成半导体结构的方法包括形成第一层硅，然后形成与硅层相邻的第二硅锗层。 然后在第二层附近形成薄的第三层硅。 然后使用常规的互补金属氧化物半导体工艺在第三层硅上形成栅极结构。 然后将沟槽形成第二层，然后将结构暴露于热气态化学蚀刻剂，例如加热的盐酸。 蚀刻剂去除硅锗，从而形成无硅结构。 此后，应用传统的CMOS处理技术来完成作为金属氧化物半导体场效应晶体管的结构，包括从氮化硅形成间隔壁，氮化硅还通过去除硅填充形成在第三层硅下面的空腔 锗。

    Semiconductor device and method of manufacturing same
    8.
    发明授权
    Semiconductor device and method of manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号：US07989296B2

    公开(公告)日：2011-08-02

    申请号：US12015646

    申请日：2008-01-17

    申请人： Sung-young Lee ,  Dong-suk Shin

    发明人： Sung-young Lee ,  Dong-suk Shin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78639 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78687

    摘要： A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.

    摘要翻译： 公开了一种半导体器件及其制造方法。 半导体器件包括形成在半导体衬底上的栅电极，形成在栅电极下方的空间的有源区，形成在栅电极和空间之间的沟道区，以及形成在栅电极的相对侧上的源极和漏极区 活跃区域。 通过在活性区域中蚀刻形成在栅电极下方的半导体层来形成空间。

    Semiconductor device with increased channel area
    9.
    发明授权
    Semiconductor device with increased channel area 失效
    半导体器件通道面积增加

    公开(公告)号：US07977749B2

    公开(公告)日：2011-07-12

    申请号：US12648227

    申请日：2009-12-28

    申请人： Jun-Hee Cho

    发明人： Jun-Hee Cho

    IPC分类号： H01L29/786 ,  H01L29/80

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78639 ,  H01L29/78696

    摘要： A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

    摘要翻译： 半导体器件包括限定至少四个表面的有源区，所述四个表面包括第一，第二，第三和第四表面，围绕有源区的四个表面形成的栅极绝缘层，以及围绕栅极绝缘体形成的栅电极 层和有源区的四个表面。