Abstract:
Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.
Abstract:
Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.
Abstract:
Semiconductor structures and methods for manufacturing the same are disclosed. The semiconductor structure comprises: a gate stack formed on a semiconductor substrate; a super-steep retrograde island embedded in said semiconductor substrate and self-aligned with said gate stack; and a counter doped region embedded in said super-steep retrograde island, wherein said counter doped region has a doping type opposite to a doping type of said super-steep retrograde island. The semiconductor structures and the methods for manufacturing the same facilitate alleviating short channel effects.
Abstract:
Semiconductor structures and methods for manufacturing the same are disclosed. The semiconductor structure comprises: a gate stack formed on a semiconductor substrate; a super-steep retrograde island embedded in said semiconductor substrate and self-aligned with said gate stack; and a counter doped region embedded in said super-steep retrograde island, wherein said counter doped region has a doping type opposite to a doping type of said super-steep retrograde island. The semiconductor structures and the methods for manufacturing the same facilitate alleviating short channel effects.
Abstract:
Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device comprises a semiconductor substrate; an insulating layer located on the semiconductor substrate; a semiconductor body located on the insulating layer; a cavity formed in the semiconductor body and into the insulating layer; source/drain regions abutting opposite first side faces of the semiconductor body; gates located on opposite second side faces of the semiconductor body; a channel layer interposed between the respective second side faces and the cavity; and a super-steep-retrograded-well and a halo super-steep-retrograded-well formed in the channel layer. The super-steep-retrograded-well and the halo super-steep-retrograded-well have opposite dopant polarities.
Abstract:
Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device comprises a semiconductor substrate; an insulating layer located on the semiconductor substrate; a semiconductor body located on the insulating layer; a cavity formed in the semiconductor body and into the insulating layer; source/drain regions abutting opposite first side faces of the semiconductor body; gates located on opposite second side faces of the semiconductor body; a channel layer interposed between the respective second side faces and the cavity; and a super-steep-retrograded-well and a halo super-steep-retrograded-well formed in the channel layer. The super-steep-retrograded-well and the halo super-steep-retrograded-well have opposite dopant polarities.
Abstract:
This invention belongs to the field of biochemical engineering and relates to a method of cyclic utilization of water during separation of succinic acid made by fermentation. This invention uses water from separation process for aerobic growth of E. coli AFP111 and production of succinic acid by anaerobic fermentation, obtaining final succinic acid concentration of 55 g/L and yield of 91.6%. Compared with results of fermentation using culture medium prepared from tap water, succinic acid concentration and productivity increased by 8.5% and 8.46%, respectively. An outstanding advantage of this invention is recovery and utilization of evaporated water during separation of succinic acid, realizing cyclic use of water during industrial production of succinic acid, which is an environment-friendly process. Also, as evaporated water generated during separation of succinic acid contains small amount of organic acids such as acetic acid and formic acid, if this water is used for aerobic growth of thalli, the small amount of organic acids contained therein can be used as gluconeogenesis carbon source, improving activity of some key enzymes in cell and favoring succinic acid production by anaerobic fermentation of thalli.
Abstract:
The present disclosure describes methods, systems, and computer program products for finding a best location scheme for a set of interactional objects in a constrained geographical area. A geographic region representing a wind farm is partitioned into a plurality of lattices. Initial chromosomes are generated, where a particular chromosome is a binary series used to represent the presence of a wind turbine in a layout of the plurality of lattices. A cost associated with each wind turbine associated with the initial chromosomes is evaluated. Parent chromosomes are selected for a genetic operation, and following the genetic operation, a cost associated with each wind turbine if evaluated. The parent chromosomes are updated using a fitness value.
Abstract:
An array substrate comprises a first metal layer in which first signal lines are disposed; a second metal layer in which second signal lines are disposed; an insulation layer provided between the first and second metal layers. A repairing line is provided in edge regions of the second metal layer and insulated from the second signal lines, and the repairing line comprises a first longitudinal portion, a second longitudinal portion and a transverse portion, the first longitudinal portion is electrically connected to the second longitudinal portion by the transverse portion. A projection of the first longitudinal portion in a plane of the first metal layer intersects with one end of each of the first signal lines, and a projection of the second longitudinal portion in the plane of the first metal layer intersects with the other end of each of the first signal lines.
Abstract:
The present invention relates to compounds of formula (I) that are useful as hepatitis C virus (HCV) NS5B polymerase inhibitors, the synthesis of such compounds, and the use of such compounds for inhibiting HCV NS5B polymerase activity, for treating or preventing HCV infections and for inhibiting HCV viral replication and/or viral production in a cell-based system.