公开(公告)号：US11995330B2

公开(公告)日：2024-05-28

申请号：US17125420

申请日：2020-12-17

申请人： Intel Corporation

发明人： Francesc Guim Bernat ,  Evan Custodio ,  Susanne M. Balle ,  Joe Grecco ,  Henry Mitchel ,  Rahul Khanna ,  Slawomir Putyrski ,  Sujoy Sen ,  Paul Dormitzer

IPC分类号： G06F3/06 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F16/174 ,  G06F21/57 ,  G06F21/62 ,  G06F21/73 ,  G06F21/76 ,  G06T1/20 ,  G06T1/60 ,  G06T9/00 ,  H01R13/453 ,  H01R13/631 ,  H03K19/173 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L9/08 ,  H04L12/28 ,  H04L12/46 ,  H04L41/044 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L49/104 ,  H04L61/5007 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/63 ,  H04L67/75 ,  H05K7/14 ,  G06F11/14 ,  G06F15/80 ,  G06F16/28 ,  H04L9/40 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L47/78 ,  H04Q11/00

CPC分类号： G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/45533 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5005 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5083 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3079 ,  G06F11/3409 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/453 ,  H01R13/4536 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L49/104 ,  H04L61/5007 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/63 ,  H04L67/75 ,  H05K7/1452 ,  H05K7/1487 ,  H05K7/1491 ,  G06F11/1453 ,  G06F12/023 ,  G06F15/80 ,  G06F16/285 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  H04L41/046 ,  H04L41/0896 ,  H04L41/142 ,  H04L47/78 ,  H04L63/1425 ,  H04Q11/0005 ,  H05K7/1447 ,  H05K7/1492

摘要： Technologies for providing accelerated functions as a service in a disaggregated architecture include a compute device that is to receive a request for an accelerated task. The task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task. The compute device is further to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request. Additionally, the compute device is to assign the task to the determined accelerator sled for execution. Other embodiments are also described and claimed.

公开(公告)号：US20180351572A1

公开(公告)日：2018-12-06

申请号：US16108896

申请日：2018-08-22

申请人： Realtime Data LLC

发明人： James J. FALLON ,  Paul F. PICKEL ,  Stephen J. MCERLAIN ,  Carlton J. MELONE, II

IPC分类号： H03M7/40 ,  H04L29/08 ,  H04L12/18 ,  G06T9/00

CPC分类号： H03M7/4006 ,  G06Q10/10 ,  G06Q40/04 ,  G06Q40/10 ,  G06T9/005 ,  H01L51/52 ,  H03M7/30 ,  H03M7/3059 ,  H04L12/1895 ,  H04L29/06027 ,  H04L29/0604 ,  H04L29/06176 ,  H04L65/4076 ,  H04L65/607 ,  H04L65/80 ,  H04L67/26 ,  H04L67/2828 ,  H04L69/04

摘要： The transmission of broadcast data, such as financial data and news feeds, is accelerated over a communication channel using data compression and decompression to provide secure transmission and transparent multiplication of communication bandwidth, as well as reduce the latency. Broadcast data may include packets having fields. Encoders associated with particular fields may be selected to compress those particular fields.

公开(公告)号：US20180278935A1

公开(公告)日：2018-09-27

申请号：US15991061

申请日：2018-05-29

申请人： Sun Patent Trust

发明人： Daisaku KOMIYA ,  Takahiro NISHI ,  Youji SHIBAHARA ,  Hisao SASAI ,  Toshiyasu SUGIO ,  Kyoko TANIKAWA ,  Toru MATSUNOBU

IPC分类号： H04N19/124 ,  H04N19/172 ,  H04N19/436 ,  G06T9/00 ,  H04N19/60 ,  H04N19/70 ,  H04N19/134 ,  H04N19/51 ,  H04N19/593 ,  H04N19/17 ,  H04N19/46 ,  H04N19/13 ,  H04N19/176 ,  H04N19/174 ,  H04N19/503

CPC分类号： H04N19/124 ,  G06T9/00 ,  G06T9/005 ,  G06T9/007 ,  G06T9/008 ,  H04N19/13 ,  H04N19/134 ,  H04N19/17 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/436 ,  H04N19/46 ,  H04N19/503 ,  H04N19/51 ,  H04N19/593 ,  H04N19/60 ,  H04N19/70

摘要： A non-transitory recording medium including a program is provided. The program causes a processor to divide a picture into tiles. The tiles are coded to generate pieces of coded data, each of which corresponds to a different one of the tiles. In this regard, a first tile of the tiles is coded with reference to coding information of an already-coded tile neighboring the first tile when a boundary between the first tile and the already-coded tile is a first boundary. The first tile is coded without reference to the coding information of the already-coded tile when the boundary between the first tile and the already-coded tile is a second boundary. A bitstream including the pieces of coded data is generated. The bitstream includes tile boundary independence information which indicates whether each boundary between the tiles is one of the first boundary and the second boundary.

公开(公告)号：US20180226987A1

公开(公告)日：2018-08-09

申请号：US15948115

申请日：2018-04-09

申请人： NTT DOCOMO, INC.

发明人： Frank Jan BOSSEN

IPC分类号： H03M7/40 ,  H04N19/91 ,  G06T9/00

CPC分类号： H03M7/4006 ,  G06T9/00 ,  G06T9/005 ,  H03M7/4012 ,  H03M7/4018 ,  H04N19/91

摘要： An arithmetic encoder is provided for converting an event sequence comprised of a plurality of events to an information sequence comprised of at least one information piece, and includes a core engine for receiving an event of the event sequence, and a probability estimate from a probability estimator, and generating zero or more pieces of the information sequence responsive to the received event and the probability estimate by bounding the ratio of events to information pieces. An arithmetic encoder is provided that is capable of constraining a number of events in at least one event sequence as a function of the number of generated information pieces in at least one information sequence. An arithmetic decoder is provided for converting an information sequence comprised of at least one information piece to an event sequence comprised of a plurality of events, and includes a core engine for processing at least one information piece of the information sequence from the sequencer responsive to a probability estimate received from a probability estimator to generate at least one event by accounting for a bounded ratio of events to information pieces in the information sequence.

公开(公告)号：US10003794B2

公开(公告)日：2018-06-19

申请号：US14360262

申请日：2012-11-22

申请人： THOMSON LICENSING

发明人： Wenfei Jiang ,  Kangying Cai ,  Yi Hu

IPC分类号： G06T17/00 ,  G06T15/00 ,  G06T9/40 ,  G06F17/30 ,  H04N19/96 ,  H04N19/91 ,  H04N13/00 ,  G06T9/00

CPC分类号： H04N19/10 ,  G06T9/005 ,  G06T17/005 ,  H04N13/161

摘要： The invention provides a method of terminable spatial tree-based position coding and decoding, and corresponding coding and decoding apparatus. The encoding method comprises: constructing a cell around the input spatial points; recursively dividing the cell into sub-cells at different layers; and assigning a symbol for each sub-cell indicating whether or not there is a spatial point within each sub-cell. The method further comprising: terminating further division of a sub-cell, if the sub-cell contains only one point and the distance between the center point of the sub-cell and the point contained in the sub-cell is smaller than the allowed maximal error.

公开(公告)号：US20180150471A1

公开(公告)日：2018-05-31

申请号：US15719774

申请日：2017-09-29

申请人： Intel Corporation

发明人： Vinodh Gopal ,  James D. Guilford ,  Kirk S. Yap ,  Simon N. Peffers ,  Daniel F. Cutter

IPC分类号： G06F17/30 ,  H03M7/30

CPC分类号： G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

摘要： Technologies for database acceleration include a computing device having a database accelerator. The database accelerator performs a decompress operation on one or more compressed elements of a compressed database to generate one or more decompressed elements. After decompression of the compressed elements, the database accelerator prepares the one or more decompressed elements to generate one or more prepared elements to be processed by an accelerated filter. The database accelerator then performs the accelerated filter on the one or more prepared elements to generate one or more output elements. Other embodiments are described and claimed.

公开(公告)号：US20180150330A1

公开(公告)日：2018-05-31

申请号：US15721833

申请日：2017-09-30

申请人： Intel Corporation

发明人： Francesc Guim Bernat ,  Evan Custodio ,  Susanne M. Balle ,  Joe Grecco ,  Henry Mitchel ,  Slawomir Putyrski

IPC分类号： G06F9/50 ,  G06F9/54 ,  H04L29/08 ,  G06F9/38

CPC分类号： G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

摘要： A compute device to manage workflow to disaggregated computing resources is provided. The compute device comprises a compute engine receive a workload processing request, the workload processing request defined by at least one request parameter, determine at least one accelerator device capable of processing a workload in accordance with the at least one request parameter, transmit a workload to the at least one accelerator device, receive a work product produced by the at least one accelerator device from the workload, and provide the work product to an application.

公开(公告)号：US20180150299A1

公开(公告)日：2018-05-31

申请号：US15721829

申请日：2017-09-30

申请人： Intel Corporation

发明人： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan Custodio ,  Rahul Khanna ,  Sujoy Sen

IPC分类号： G06F9/38 ,  G06F12/02 ,  G06T1/20 ,  G06T1/60

CPC分类号： G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

摘要： Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

公开(公告)号：US20180097970A1

公开(公告)日：2018-04-05

申请号：US15790360

申请日：2017-10-23

申请人： Kyocera Document Solutions Inc.

发明人： Hideo Nakahara

IPC分类号： H04N1/417 ,  H04N19/597

CPC分类号： H04N1/4175 ,  G06K15/1817 ,  G06K15/1822 ,  G06K15/1842 ,  G06K15/1843 ,  G06K15/1857 ,  G06T9/005 ,  H04N1/41 ,  H04N1/642 ,  H04N19/436 ,  H04N19/44 ,  H04N19/597

摘要： A method using L processers includes: receiving image data encoded by delta row encoding; dividing the two dimensionally arranged plurality of pixels by M (M≦L) to make M blocks of pixels; assigning M processers to perform a parallel processing of accumulating the delta data for all the row lines of each of the M blocks of the image data to obtain the accumulated delta data, the accumulated delta data including a total delta between the first row line and the last row line in each of the blocks; obtaining the first row lines in the respective blocks using the total delta one by one starting from the second block; and assigning M+1 processers to perform a parallel processing of decoding using the obtained first row lines to obtain the decoded data and a parallel processing of rendering the image data using the decoded data.

公开(公告)号：US20180084258A1

公开(公告)日：2018-03-22

申请号：US15829073

申请日：2017-12-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Woo-shik KIM ,  Chang-yeong KIM ,  Yang-seock SEO

IPC分类号： H04N19/159 ,  H04N19/11 ,  H04N19/122 ,  H04N19/105 ,  H04N19/182 ,  H04N19/184 ,  H04N19/186 ,  H04N19/176

CPC分类号： H04N19/159 ,  G06T9/004 ,  G06T9/005 ,  H04N19/105 ,  H04N19/11 ,  H04N19/122 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/184 ,  H04N19/186 ,  H04N19/44 ,  H04N19/593 ,  H04N19/61

摘要： A coding method including dividing pixels of a chrominance component of an input image into blocks having a predetermined size; selecting one among a direct current prediction method, a vertical prediction method, a horizontal prediction method, and a hybrid prediction method according to a user's input; generating a prediction value of each pixel in a current block to be predictively coded, using at least one pixel value among pixel values in an upper reference block adjacent to the current block and in a side reference block adjacent to the current block, according to the selected prediction method; generating a differential value between the prediction value and a corresponding real pixel value in the current block; and coding the differential value and information on the selected prediction method using a predetermined coding method.