公开(公告)号：US20210384222A1

公开(公告)日：2021-12-09

申请号：US17406157

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Ji-su Yu ,  Hyeon-gyu You ,  Seung-young Lee ,  Jae-boong Lee

IPC: H01L27/118 ,  H01L27/02 ,  G06F30/39

Abstract: An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.

公开(公告)号：US10579771B2

公开(公告)日：2020-03-03

申请号：US15933958

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Jong-hoon Jung ,  Ji-su Yu ,  Seung-young Lee ,  Tae-joong Song ,  Jae-boong Lee

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US11164863B2

公开(公告)日：2021-11-02

申请号：US16732670

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Sang-hoon Baek ,  Tae-joong Song ,  Jong-hoon Jung ,  Seung-young Lee

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L27/07 ,  H01L27/02 ,  H01L29/417 ,  H01L23/522 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/8234

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

公开(公告)号：US11152392B2

公开(公告)日：2021-10-19

申请号：US17034602

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Ji-Su Yu ,  Hyeon-gyu You ,  Seung-Young Lee ,  Jae-boong Lee ,  Jong-hoon Jung

IPC: H01L23/52 ,  H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.

公开(公告)号：US10177087B2

公开(公告)日：2019-01-08

申请号：US15493279

申请日：2017-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vincent Chun Fai Lau ,  Jung-ho Do ,  Byung-sung Kim ,  Chul-hong Park

IPC: H01L27/088 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

公开(公告)号：US09653394B2

公开(公告)日：2017-05-16

申请号：US14619073

申请日：2015-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vincent Chun Fai Lau ,  Jung-ho Do ,  Byung-sung Kim ,  Chul-hong Park

IPC: H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

公开(公告)号：US11437315B2

公开(公告)日：2022-09-06

申请号：US16774082

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/118 ,  H01L23/522 ,  H01L27/092 ,  H01L27/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US11289469B2

公开(公告)日：2022-03-29

申请号：US17038292

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Young Lee ,  Jong-hoon Jung ,  Myoung-ho Kang ,  Jung-ho Do

IPC: H01L27/02 ,  G11C11/419 ,  G11C11/40 ,  H01L23/528 ,  H01L27/105 ,  H01L27/118 ,  G11C5/14 ,  G11C7/18

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

公开(公告)号：US11121155B2

公开(公告)日：2021-09-14

申请号：US16292433

申请日：2019-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Ji-su Yu ,  Hyeon-gyu You ,  Seung-young Lee ,  Jae-boong Lee

IPC: H01L27/118 ,  H01L23/52 ,  H01L21/82 ,  H01L27/02 ,  G06F30/39

Abstract: An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.

公开(公告)号：US10573643B2

公开(公告)日：2020-02-25

申请号：US15686795

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Sang-hoon Baek ,  Tae-joong Song ,  Jong-hoon Jung ,  Seung-young Lee

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L27/07 ,  H01L27/02 ,  H01L29/417 ,  H01L23/522 ,  H01L29/08 ,  H01L29/10

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.