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    Logic cell including deep via contact and wiring layers located at different levels
    2.
    发明授权
    Logic cell including deep via contact and wiring layers located at different levels 有权

    公开(公告)号：US10707163B2

    公开(公告)日：2020-07-07

    申请号：US16200747

    申请日：2018-11-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Vincent Chun Fai Lau ,  Jung-ho Do ,  Byung-sung Kim ,  Chul-hong Park

    IPC: H01L23/522 ,  H01L27/088 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528

    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

    Integrated circuit and standard cell library
    3.
    发明授权
    Integrated circuit and standard cell library 有权

    公开(公告)号：US10720429B2

    公开(公告)日：2020-07-21

    申请号：US16390431

    申请日：2019-04-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Deepak Sharma ,  Hyun-jong Lee ,  Raheel Azmat ,  Chul-hong Park ,  Sang-jun Park

    IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

    INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF FABRICATING THE INTEGRATED CIRCUIT
    4.
    发明申请
    INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF FABRICATING THE INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200057830A1

    公开(公告)日：2020-02-20

    申请号：US16401820

    申请日：2019-05-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Sidharth Rastogi ,  Chul-hong Park ,  Jae-seok Yang ,  Kwan-young Chun

    IPC: G06F17/50 ,  H01L27/02

    Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

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