公开(公告)号：US20230068716A1

公开(公告)日：2023-03-02

申请号：US17751093

申请日：2022-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungju Kang ,  Raheel Azmat ,  Jiwook Kwon ,  Suhyeon Kim ,  Kwanyoung Chun

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/394 ,  H01L23/528 ,  H01L23/522 ,  H01L27/118

Abstract: A semiconductor device includes: a standard cell including a plurality of active patterns extending in a first direction, a gate structure intersecting the plurality of active patterns and extending in a second direction, and source/drain regions respectively provided on the plurality of active patterns positioned on both sides of the gate structure; a plurality of signal lines extending on the standard cell in the first direction, arranged in the second direction, and electrically connected to the standard cell; and first and second power straps extending on the standard cell in the first direction, electrically connected to some of the source/drain regions, and supplying power to the standard cell, wherein each of the first and second power straps is provided on the standard cell while provided on the same line as any one of the plurality of signal lines in the first direction.

公开(公告)号：US20210183859A1

公开(公告)日：2021-06-17

申请号：US16997335

申请日：2020-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Jeong ,  Raheel Azmat

IPC: H01L27/092 ,  H01L27/02

Abstract: A semiconductor integrated circuit includes a substrate, and a standard cell on the substrate. The standard cell includes a first wiring structure electrically connecting a first gate pattern to a fourth gate pattern, and a second wiring structure electrically connecting a second gate pattern to a third gate pattern. The first wiring structure includes a first lower wiring layer, a second lower wiring layer, first and second intermediate wiring layers, and a first upper wiring layer. The second wiring structure includes a third lower wiring layer, a fourth lower wiring layer, third and fourth intermediate wiring layers, and a second upper wiring layer.

公开(公告)号：US10720429B2

公开(公告)日：2020-07-21

申请号：US16390431

申请日：2019-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak Sharma ,  Hyun-jong Lee ,  Raheel Azmat ,  Chul-hong Park ,  Sang-jun Park

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

公开(公告)号：US20200057830A1

公开(公告)日：2020-02-20

申请号：US16401820

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sidharth Rastogi ,  Chul-hong Park ,  Jae-seok Yang ,  Kwan-young Chun

IPC: G06F17/50 ,  H01L27/02

Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

公开(公告)号：US10002860B2

公开(公告)日：2018-06-19

申请号：US15380770

申请日：2016-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raheel Azmat

IPC: H01L23/52 ,  H01L27/02 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/11807 ,  H01L2027/11881

Abstract: An integrated circuit includes at least one cell. The at least one cell includes a cell region defined by a cell boundary; a power line structure extending in a first direction parallel to and along the cell boundary and including a first power line extending in the first direction along the cell boundary, a plurality of metal islands spaced apart from one another over the first power line in the first direction, and a second power line extending in the first direction over the plurality of metal islands; and a signal line structure disposed in the cell region at the same level as the first power line and the plurality of metal islands. Separation distances between each of the plurality of metal islands and a part of the signal line structure at the same level as the plurality of metal islands are equal to or greater than a critical separation distance.

公开(公告)号：US11868691B2

公开(公告)日：2024-01-09

申请号：US17944379

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sidharth Rastogi ,  Chul-hong Park ,  Jae-seok Yang ,  Kwan-young Chun

IPC: G06F30/327 ,  H01L27/02 ,  G06F30/398

CPC classification number: G06F30/327 ,  G06F30/398 ,  H01L27/0207

Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

公开(公告)号：US10903213B2

公开(公告)日：2021-01-26

申请号：US16453645

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sidharth Rastogi ,  Subhash Kuchanuri ,  Raheel Azmat ,  Pan-jae Park ,  Chul-hong Park ,  Jae-seok Yang ,  Kwan-young Chun

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/76 ,  H01L21/768 ,  H01L23/535 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/118

Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.

公开(公告)号：US10224331B2

公开(公告)日：2019-03-05

申请号：US15911922

申请日：2018-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raheel Azmat ,  Deepak Sharma ,  Su-Hyeon Kim ,  Chulhong Park

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L29/775

Abstract: Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

公开(公告)号：US10170421B2

公开(公告)日：2019-01-01

申请号：US15647467

申请日：2017-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta Rwik ,  Su-Hyeon Kim ,  Chul-Hong Park ,  Jae-Hyoung Lim

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L29/00 ,  H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

公开(公告)号：US09947661B2

公开(公告)日：2018-04-17

申请号：US15641417

申请日：2017-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sharma Deepak ,  Chulhong Park

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/8238 ,  H01L23/522 ,  H01L29/08 ,  H01L29/06 ,  H01L23/528 ,  H01L27/118 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.