公开(公告)号：US10402528B2

公开(公告)日：2019-09-03

申请号：US14966264

申请日：2015-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Su-Hyeon Kim ,  Sharma Deepak

IPC: G06F17/50

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

公开(公告)号：US10224331B2

公开(公告)日：2019-03-05

申请号：US15911922

申请日：2018-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raheel Azmat ,  Deepak Sharma ,  Su-Hyeon Kim ,  Chulhong Park

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L29/775

Abstract: Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

公开(公告)号：US10170421B2

公开(公告)日：2019-01-01

申请号：US15647467

申请日：2017-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta Rwik ,  Su-Hyeon Kim ,  Chul-Hong Park ,  Jae-Hyoung Lim

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L29/00 ,  H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

公开(公告)号：US09965579B2

公开(公告)日：2018-05-08

申请号：US14690227

申请日：2015-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Sang-Hoon Baek ,  Su-Hyeon Kim ,  Kyoung-Yun Baek ,  Sung-Wook Ahn ,  Sang-Kyu Oh ,  Seung-Jae Jung

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

公开(公告)号：US09741661B2

公开(公告)日：2017-08-22

申请号：US15188743

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta Rwik ,  Su-Hyeon Kim ,  Chul-Hong Park ,  Jae-Hyoung Lim

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L29/00 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L23/5286 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

公开(公告)号：US10699052B2

公开(公告)日：2020-06-30

申请号：US16528714

申请日：2019-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Su-Hyeon Kim ,  Sharma Deepak

IPC: G06F17/50 ,  G06F30/392 ,  G06F30/398

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

公开(公告)号：US20190354655A1

公开(公告)日：2019-11-21

申请号：US16528714

申请日：2019-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Su-Hyeon Kim ,  Sharma Deepak

IPC: G06F17/50

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.