公开(公告)号：US09965579B2

公开(公告)日：2018-05-08

申请号：US14690227

申请日：2015-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Sang-Hoon Baek ,  Su-Hyeon Kim ,  Kyoung-Yun Baek ,  Sung-Wook Ahn ,  Sang-Kyu Oh ,  Seung-Jae Jung

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.