公开(公告)号：US10950724B2

公开(公告)日：2021-03-16

申请号：US16364303

申请日：2019-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeoncheol Heo ,  Sharma Deepak ,  Kwanyoung Chun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.

公开(公告)号：US10402528B2

公开(公告)日：2019-09-03

申请号：US14966264

申请日：2015-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Su-Hyeon Kim ,  Sharma Deepak

IPC: G06F17/50

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

公开(公告)号：US09947661B2

公开(公告)日：2018-04-17

申请号：US15641417

申请日：2017-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sharma Deepak ,  Chulhong Park

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/8238 ,  H01L23/522 ,  H01L29/08 ,  H01L29/06 ,  H01L23/528 ,  H01L27/118 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

公开(公告)号：US10297687B2

公开(公告)日：2019-05-21

申请号：US15821116

申请日：2017-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeoncheol Heo ,  Sharma Deepak ,  Kwanyoung Chun

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/02

Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.

公开(公告)号：US20180151728A1

公开(公告)日：2018-05-31

申请号：US15821116

申请日：2017-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeoncheol Heo ,  Sharma Deepak ,  Kwanyoung Chun

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42392

Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.

公开(公告)号：US20170309627A1

公开(公告)日：2017-10-26

申请号：US15641417

申请日：2017-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel AZMAT ,  Sharma Deepak ,  Chulhong Park

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/118

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

公开(公告)号：US09748238B2

公开(公告)日：2017-08-29

申请号：US15206610

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sharma Deepak ,  Chulhong Park

IPC: H01L27/08 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L27/118 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

公开(公告)号：US10699052B2

公开(公告)日：2020-06-30

申请号：US16528714

申请日：2019-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Su-Hyeon Kim ,  Sharma Deepak

IPC: G06F17/50 ,  G06F30/392 ,  G06F30/398

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

公开(公告)号：US20190354655A1

公开(公告)日：2019-11-21

申请号：US16528714

申请日：2019-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Su-Hyeon Kim ,  Sharma Deepak

IPC: G06F17/50

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

公开(公告)号：US20190288109A1

公开(公告)日：2019-09-19

申请号：US16364303

申请日：2019-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeoncheol Heo ,  Sharma Deepak ,  Kwanyoung Chun

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02 ,  H01L29/06

Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.