公开(公告)号：US11164863B2

公开(公告)日：2021-11-02

申请号：US16732670

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Sang-hoon Baek ,  Tae-joong Song ,  Jong-hoon Jung ,  Seung-young Lee

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L27/07 ,  H01L27/02 ,  H01L29/417 ,  H01L23/522 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/8234

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

公开(公告)号：US20160055286A1

公开(公告)日：2016-02-25

申请号：US14820983

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Sang-kyu Oh ,  Seung-young Lee

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G03F1/00 ,  G06F17/5072 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Abstract translation: 设计集成芯片（IC）的布局的方法包括通过放置和布线定义IC的多个标准单元来设计第一布局，以及通过在与...相关的掩模数据准备处理过程中修改第一布局来生成第二布局 第一布局，其中通过连接与第一布局的第一层相对应的第一层图案中的第一和第二图案来生成第二布局，使得形成第一层图案所需的掩模的数量减少。

公开(公告)号：US20210384222A1

公开(公告)日：2021-12-09

申请号：US17406157

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Ji-su Yu ,  Hyeon-gyu You ,  Seung-young Lee ,  Jae-boong Lee

IPC: H01L27/118 ,  H01L27/02 ,  G06F30/39

Abstract: An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.

公开(公告)号：US10579771B2

公开(公告)日：2020-03-03

申请号：US15933958

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Jong-hoon Jung ,  Ji-su Yu ,  Seung-young Lee ,  Tae-joong Song ,  Jae-boong Lee

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US09716106B2

公开(公告)日：2017-07-25

申请号：US15232223

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Sang-kyu Oh ,  Jung-Ho Do ,  Sun-young Park ,  Seung-young Lee ,  Hyo-sig Won

IPC: H01L27/118 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/6681 ,  H01L29/785 ,  H01L2027/11875

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

公开(公告)号：US12136626B2

公开(公告)日：2024-11-05

申请号：US17406157

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Ji-su Yu ,  Hyeon-gyu You ,  Seung-young Lee ,  Jae-boong Lee

IPC: H01L27/118 ,  G06F30/39 ,  H01L27/02

Abstract: An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.

公开(公告)号：US20190355749A1

公开(公告)日：2019-11-21

申请号：US16292433

申请日：2019-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Ji-su Yu ,  Hyeon-gyu You ,  Seung-young Lee ,  Jae-boong Lee

IPC: H01L27/118 ,  H01L27/02 ,  G06F17/50

Abstract: An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.

公开(公告)号：US20180175024A1

公开(公告)日：2018-06-21

申请号：US15686795

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO ,  Sang-hoon Baek ,  Tae-joong Song ,  Jong-hoon Jung ,  Seung-young Lee

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L27/07 ,  H01L27/02 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L27/088 ,  H01L21/823487 ,  H01L21/823885 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/7827

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

公开(公告)号：US11042686B2

公开(公告)日：2021-06-22

申请号：US16750501

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Jong-hoon Jung ,  Ji-Su Yu ,  Seung-young Lee ,  Tae-joong Song ,  Jae-boong Lee

IPC: G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/392

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US10804257B2

公开(公告)日：2020-10-13

申请号：US16685471

申请日：2019-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-young Lee ,  Jong-hoon Jung ,  Myoung-ho Kang ,  Jung-ho Do

IPC: H01L27/02 ,  G11C11/419 ,  G11C11/40 ,  H01L23/528 ,  H01L27/105 ,  H01L27/118 ,  G11C5/14 ,  G11C7/18

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.