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48 条记录 (耗时 0.017 秒)

    System on chip
    1.
    发明授权
    System on chip 有权

    公开(公告)号：US11201150B2

    公开(公告)日：2021-12-14

    申请号：US16746071

    申请日：2020-01-17

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L23/528

    摘要： A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10050058B2

    公开(公告)日：2018-08-14

    申请号：US15282206

    申请日：2016-09-30

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Taejoong Song ,  Ha-Young Kim ,  Jung-Ho Do ,  Sanghoon Baek ,  Jinyoung Lim ,  Kwangok Jeong

    IPC分类号： H01L21/8238 ,  H01L27/118 ,  G06F17/50 ,  G03F1/36 ,  H01L21/66 ,  H01L27/02 ,  H01L27/092 ,  H01L27/11582

    摘要： A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

    INTEGRATED CIRCUIT INCLUDING A MODIFIED CELL AND A METHOD OF DESIGNING THE SAME
    5.
    发明申请
    INTEGRATED CIRCUIT INCLUDING A MODIFIED CELL AND A METHOD OF DESIGNING THE SAME 审中-公开

    公开(公告)号：US20180096092A1

    公开(公告)日：2018-04-05

    申请号：US15585548

    申请日：2017-05-03

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： JIN-TAE KIM ,  Jung-Ho Do ,  Tae-Joong Song ,  Doo-Hee Cho ,  Seung-Young Lee

    IPC分类号： G06F17/50

    摘要： A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.

    Semiconductor device including a field effect transistor
    7.
    发明授权
    Semiconductor device including a field effect transistor 有权

    公开(公告)号：US10916535B2

    公开(公告)日：2021-02-09

    申请号：US16727280

    申请日：2019-12-26

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jung-Ho Do ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

    IPC分类号： H01L27/02 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  H01L27/118 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/092 ,  G06F30/398 ,  G06F119/18

    摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

    System on chip
    10.
    发明授权
    System on chip 有权

    公开(公告)号：US10541237B2

    公开(公告)日：2020-01-21

    申请号：US16037581

    申请日：2018-07-17

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234 ,  H01L23/528

    摘要： A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.