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    Semiconductor devices and methods of fabricating the same
    1.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权

    公开(公告)号：US10211091B2

    公开(公告)日：2019-02-19

    申请号：US15334469

    申请日：2016-10-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

    IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/108

    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

    Nonvolatile memory device
    2.
    发明授权
    Nonvolatile memory device 有权

    公开(公告)号：US10985213B2

    公开(公告)日：2021-04-20

    申请号：US16780014

    申请日：2020-02-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Si-Ho Song ,  Youngbae Kim ,  Dueung Kim ,  Changhyun Cho

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    Abstract: A nonvolatile memory device includes a memory cell array, a word line drive block that is connected to a first group of memory cells through a first group of word lines and to a second group of memory cells through a second group of word lines, a bit line bias and sense block that is connected to the first and second groups of memory cells through bit lines, a variable current supply block that generates a word line current to be supplied to a selected word line, and a control logic block that receives an address and a command and controls the variable current supply block to adjust an amount of the word line current based on the address. The control logic block further varies the amount of the word line current depending on a distance between the selected word line and the substrate.

    Three dimensional semiconductor memory devices
    3.
    发明授权
    Three dimensional semiconductor memory devices 有权

    公开(公告)号：US11665914B2

    公开(公告)日：2023-05-30

    申请号：US17406166

    申请日：2021-08-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Si-Ho Song ,  Jeonghee Park ,  Changhyun Cho

    IPC: H01L27/24 ,  H01L45/00 ,  G11C5/06

    CPC classification number: H01L27/249 ,  G11C5/063 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/141

    Abstract: A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and the second conductive line, and a third electrode between the first variable resistance pattern and the second variable resistance pattern.

    Semiconductor devices and methods of fabricating the same
    4.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权

    公开(公告)号：US10796950B2

    公开(公告)日：2020-10-06

    申请号：US16238172

    申请日：2019-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

    IPC: H01L21/76 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

    Three dimensional semiconductor memory devices
    6.
    发明授权
    Three dimensional semiconductor memory devices 有权

    公开(公告)号：US11127792B2

    公开(公告)日：2021-09-21

    申请号：US16710450

    申请日：2019-12-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Si-Ho Song ,  Jeonghee Park ,  Changhyun Cho

    IPC: H01L27/24 ,  H01L45/00 ,  G11C5/06

    Abstract: A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and the second conductive line, and a third electrode between the first variable resistance pattern and the second variable resistance pattern.

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