公开(公告)号：US20170098619A1

公开(公告)日：2017-04-06

申请号：US15284921

申请日：2016-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Kyehee Yeom

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0391 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/06155 ,  H01L2224/06158 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same are provided. The semiconductor chip includes an integrated circuit on a substrate, a pad electrically connected to the integrated circuit, a lower insulating structure having a contact hole exposing the pad, and a conductive pattern including a contact portion filling the contact hole, a conductive line portion provided on the lower insulating structure to extend in a specific direction, and a bonding pad portion. The contact portion has a first thickness in a direction substantially perpendicular to a top surface of the substrate and a second thickness in another direction substantially parallel to the top surface of the substrate, the first thickness is greater than the second thickness, and the lower insulating structure includes a plurality of air gaps formed therein.

公开(公告)号：US11502082B2

公开(公告)日：2022-11-15

申请号：US16902338

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

公开(公告)号：US10714478B2

公开(公告)日：2020-07-14

申请号：US16532857

申请日：2019-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

公开(公告)号：US09607994B2

公开(公告)日：2017-03-28

申请号：US14755690

申请日：2015-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunnam Kim ,  Sunyoung Park ,  Kyehee Yeom ,  Hyeon-Woo Jang ,  Jin-Won Jeong ,  Changhyun Cho ,  HyeongSun Hong

IPC: H01L27/108 ,  H01L21/265 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/26513 ,  H01L21/7682 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.