公开(公告)号：US11502082B2

公开(公告)日：2022-11-15

申请号：US16902338

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

公开(公告)号：US10714478B2

公开(公告)日：2020-07-14

申请号：US16532857

申请日：2019-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.