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    Method of fabricating semiconductor memory device having protruding contact portion
    1.
    发明授权
    Method of fabricating semiconductor memory device having protruding contact portion 有权

    公开(公告)号：US12279415B2

    公开(公告)日：2025-04-15

    申请号：US18337134

    申请日：2023-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

    IPC: H10B12/00 ,  G11C5/12

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230039205A1

    公开(公告)日：2023-02-09

    申请号：US17723747

    申请日：2022-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-sik Park ,  Joonsuk Park ,  Jihoon Chang

    IPC: H01L27/108

    Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The method comprises providing a substrate including a cell array region and a boundary region, forming a device isolation layer that defines active sections on an upper portion of the substrate on the cell array region, forming an intermediate layer on the substrate on the boundary region, forming on the substrate an electrode layer that covers the intermediate layer on the boundary region, forming a capping layer on the electrode layer, forming an additional capping pattern including providing a first step difference to the capping layer on the boundary region, and allowing the additional capping pattern, the capping layer, and the electrode layer to proceed an etching process to form bit lines that run across the active sections. During the etching process, the electrode layer is simultaneously exposed on the cell array region and the boundary region.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权

    公开(公告)号：US20220028860A1

    公开(公告)日：2022-01-27

    申请号：US17192084

    申请日：2021-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    Semiconductor memory device and method for fabricating the same
    4.
    发明授权
    Semiconductor memory device and method for fabricating the same 有权

    公开(公告)号：US12016176B2

    公开(公告)日：2024-06-18

    申请号：US17368130

    申请日：2021-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon-Woo Jang ,  Soo Ho Shin

    IPC: H10B12/00

    CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34

    Abstract: A semiconductor memory device comprises a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including an active region defined by an element separation film, a storage pad connected to the active region of the cell region, a peri gate structure placed on the substrate of the peri region, a peri contact plug placed on both sides of the peri gate structure and connected to the substrate, a first interlayer insulating film which is placed on the storage pad and the pen contact plug, and includes a nitride-based insulating material, and an information storage unit connected to the storage pad, wherein a thickness of the first interlayer insulating film on an upper surface of the storage pad is smaller than a thickness of the first interlayer insulating film on an upper surface of the peri contact plug.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230337415A1

    公开(公告)日：2023-10-19

    申请号：US18337134

    申请日：2023-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/0335

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09472617B2

    公开(公告)日：2016-10-18

    申请号：US14604339

    申请日：2015-01-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon-Woo Jang

    IPC: H01L29/78 ,  H01L29/06 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L27/108 ,  H01L27/12

    CPC classification number: H01L29/0653 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a semiconductor device. The semiconductor device includes an isolation region disposed in a semiconductor substrate and configured to define an active region. A gate electrode buried in the active region is disposed. A gate dielectric layer is disposed between the active region and the gate electrode. A first source/drain region and a second source/drain region are disposed in the active region on both sides of the gate electrodes. An interconnection structure intersecting with the gate electrode, overlapping the first and second source/drain regions, electrically connected with the first source/drain region, and spaced apart from the second source/drain region is disposed. A contact structure is disposed on the second source/drain region.

    Abstract translation: 提供一种半导体器件。 半导体器件包括设置在半导体衬底中并被配置为限定有源区的隔离区。 设置埋在有源区中的栅电极。 栅介质层设置在有源区和栅电极之间。 第一源极/漏极区域和第二源极/漏极区域设置在栅电极两侧的有源区域中。 设置与栅电极相交的与第一和第二源极/漏极区重叠的互连结构，与第一源极/漏极区电连接并且与第二源极/漏极区域间隔开。 接触结构设置在第二源极/漏极区域上。

    Semiconductor memory devices having protruding contact portions
    7.
    发明授权
    Semiconductor memory devices having protruding contact portions 有权

    公开(公告)号：US11723191B2

    公开(公告)日：2023-08-08

    申请号：US17192084

    申请日：2021-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    Semiconductor device and method of fabricating the same
    9.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US11495533B2

    公开(公告)日：2022-11-08

    申请号：US17153963

    申请日：2021-01-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jihoon Chang ,  Jimin Choi ,  Yeonjin Lee ,  Hyeon-Woo Jang ,  Jung-Hoon Han

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

    Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

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