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公开(公告)号:US11917815B2
公开(公告)日:2024-02-27
申请号:US18123736
申请日:2023-03-20
发明人: Hyosub Kim , Keunnam Kim , Dongoh Kim , Bongsoo Kim , Euna Kim , Chansic Yoon , Kiseok Lee , Hyeonok Jung , Sunghee Han , Yoosang Hwang
IPC分类号: H10B12/00 , H01L27/108 , H01L23/528
CPC分类号: H10B12/315 , H01L23/5283 , H10B12/053 , H10B12/34 , H10B12/482 , H10B12/485 , H10B12/488
摘要: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.
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公开(公告)号:US11889681B2
公开(公告)日:2024-01-30
申请号:US17720664
申请日:2022-04-14
发明人: Taejin Park , Taehoon Kim , Kyujin Kim , Chulkwon Park , Sunghee Han , Yoosang Hwang
IPC分类号: H10B12/00
CPC分类号: H10B12/34 , H10B12/053 , H10B12/315 , H10B12/482
摘要: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.
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公开(公告)号:US20230309293A1
公开(公告)日:2023-09-28
申请号:US18327920
申请日:2023-06-02
发明人: HYOSUB KIM , Keunnam Kim , Manbok Kim , Soojeong Kim , Chulkwon Park , Seungbae Jeon , Yoosang Hwang
IPC分类号: H10B12/00
CPC分类号: H10B12/315 , H10B12/34 , H10B12/053 , H10B12/0335 , H10B12/482
摘要: Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.
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公开(公告)号:US11765905B2
公开(公告)日:2023-09-19
申请号:US17185168
申请日:2021-02-25
发明人: Hyungeun Choi , Jong-ho Moon , Han-sik Yoo , Kiseok Lee , Sung-hwan Jang , Seungjae Jung , Euichul Jeong , Taehyun An , Sangyeon Han , Yoosang Hwang
IPC分类号: H10B43/40 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/20 , H10B41/40 , H10B43/10 , H10B43/20
CPC分类号: H10B43/40 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B41/20 , H10B41/40 , H10B43/10 , H10B43/20
摘要: A semiconductor memory device may include a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and are vertically stacked; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a penetration plug spaced apart from the stack and is provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuits of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad.
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公开(公告)号:US11744063B2
公开(公告)日:2023-08-29
申请号:US17374624
申请日:2021-07-13
发明人: Daeik Kim , Semyeong Jang , Jemin Park , Yoosang Hwang
IPC分类号: H01L21/71 , H01L21/28 , H01L29/792 , H01L21/8234 , H10B12/00
CPC分类号: H10B12/482 , H01L21/71 , H01L29/40114 , H01L29/7926 , H10B12/053 , H10B12/31 , H10B12/315 , H10B12/34 , H10B12/48 , H01L21/823475
摘要: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.
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公开(公告)号:US11723191B2
公开(公告)日:2023-08-08
申请号:US17192084
申请日:2021-03-04
发明人: Minsu Choi , Myeong-Dong Lee , Hyeon-Woo Jang , Keunnam Kim , Sooho Shin , Yoosang Hwang
IPC分类号: H10B12/00
CPC分类号: H10B12/34 , H10B12/0335 , H10B12/053 , H10B12/315
摘要: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.
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公开(公告)号:US20230232618A1
公开(公告)日:2023-07-20
申请号:US18123736
申请日:2023-03-20
发明人: Hyosub Kim , Keunnam Kim , Dongoh Kim , Bongsoo Kim , Euna Kim , Chansic Yoon , Kiseok Lee , Hyeonok Jung , Sunghee Han , Yoosang Hwang
IPC分类号: H10B12/00
CPC分类号: H10B12/488 , H10B12/34 , H10B12/053 , H10B12/315 , H10B12/482
摘要: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.
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公开(公告)号:US11282787B2
公开(公告)日:2022-03-22
申请号:US16879009
申请日:2020-05-20
发明人: Taejin Park , Keunnam Kim , Sohyun Park , Jin-Hwan Chun , Wooyoung Choi , Sunghee Han , Inkyoung Heo , Yoosang Hwang
IPC分类号: H01L29/40 , H01L23/48 , H01L23/52 , H01L23/528 , H01L29/06 , G11C5/10 , H01L29/423 , H01L27/108 , H01L21/768
摘要: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.
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公开(公告)号:US20210343724A1
公开(公告)日:2021-11-04
申请号:US17374624
申请日:2021-07-13
发明人: Daeik Kim , Semyeong Jang , Jemin Park , Yoosang Hwang
IPC分类号: H01L27/108 , H01L29/792 , H01L21/71 , H01L21/28
摘要: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.
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公开(公告)号:US20210066305A1
公开(公告)日:2021-03-04
申请号:US16896470
申请日:2020-06-09
发明人: Hyosub Kim , Keunnam Kim , Dongoh Kim , Bongsoo Kim , Euna Kim , Chansic Yoon , Kiseok Lee , Hyeonok Jung , Sunghee Han , Yoosang Hwang
IPC分类号: H01L27/108 , H01L23/528
摘要: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.
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