公开(公告)号：US11735588B2

公开(公告)日：2023-08-22

申请号：US16663574

申请日：2019-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Sic Yoon ,  Dongoh Kim

IPC: H01L27/092 ,  H01L21/762 ,  H10B12/00 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L27/092 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823828 ,  H10B12/09

Abstract: A semiconductor device includes a substrate having a first region and a second region. A device isolation layer is disposed in the substrate between the first region and the second region. The device isolation layer includes a buried dielectric layer in a trench that is recessed from a top surface of the substrate. A first liner layer is between the trench and the buried dielectric layer. A semiconductor layer is disposed on a top surface of the substrate of the first region. A first gate pattern is disposed on the semiconductor layer. A protrusion is disposed on a top surface of the device isolation layer.

公开(公告)号：US11696434B2

公开(公告)日：2023-07-04

申请号：US17241860

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Kyunghwan Lee ,  Dongoh Kim ,  Yongseok Kim ,  Hui-Jung Kim ,  Min Hee Cho

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/395 ,  H10B12/50

Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

公开(公告)号：US11521977B2

公开(公告)日：2022-12-06

申请号：US17471824

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US11843039B2

公开(公告)日：2023-12-12

申请号：US18074125

申请日：2022-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doosan Back ,  Dongoh Kim ,  Gyuhyun Kil ,  Jung-Hoon Han

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L29/42368 ,  H01L29/41725 ,  H01L29/513

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

公开(公告)号：US11792976B2

公开(公告)日：2023-10-17

申请号：US17371558

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongoh Kim ,  Gyuhyun Kil ,  Junghoon Han ,  Doosan Back

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.

公开(公告)号：US11320875B2

公开(公告)日：2022-05-03

申请号：US17002167

申请日：2020-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchan Lee ,  Dongoh Kim ,  Youngchan Lee ,  Jiseok Jung ,  Minwoo Cha ,  Yoongoo Han

IPC: G06F1/20 ,  H05K7/20 ,  G06F1/18

Abstract: Provided is a display device. The display device includes a housing including a front glass and a rear cover, a display panel arranged within the housing, and an air circulator arranged behind the display panel for circulating air between the front glass and the front surface of the display panel, wherein the air circulator includes a circulation fan circulating air, a case receiving the circulation fan and having open top to discharge air in a direction of long edges of the display panel, a first connection part formed to be open at one end of the case in the direction of long edges, and a second connection part formed to be open at the other end of the case in the direction of long edges.

公开(公告)号：US10910363B2

公开(公告)日：2021-02-02

申请号：US16288590

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Dongoh Kim ,  Myeong-Dong Lee

IPC: H01L21/70 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L27/24 ,  H01L27/108 ,  H01L27/22

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

公开(公告)号：US10748910B2

公开(公告)日：2020-08-18

申请号：US16053315

申请日：2018-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Sic Yoon ,  Dongoh Kim ,  Kiseok Lee ,  Sunghak Cho ,  Jemin Park

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/311

Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.

公开(公告)号：US20230412939A1

公开(公告)日：2023-12-21

申请号：US18121804

申请日：2023-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGWOO LEE ,  Eun-ji Yong ,  Dongoh Kim ,  Sungsu Kim

IPC: H04N25/62 ,  H04N25/78

CPC classification number: H04N25/62 ,  H04N25/78

Abstract: An image sensor includes a pixel unit including a plurality of pixels, and configured to generate an analog signal using the plurality of pixels, a data converter configured to receive the analog signal and convert the analog signal into a digital signal, and at least one processor configured to generate image data by performing crosstalk correction and remosaic on the digital signal, output the image data to an external device, receive image data information from the external device, determine a saturation ratio based on the image data information, and adjust settings of the remosaic based on the saturation ratio.

公开(公告)号：US11616066B2

公开(公告)日：2023-03-28

申请号：US17384347

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.