公开(公告)号：US11735532B2

公开(公告)日：2023-08-22

申请号：US17664132

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Doohwan Lee ,  Taeho Ko ,  Bongsoo Kim ,  Seokbong Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01P3/08 ,  H01P11/00 ,  H01L23/29

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01P3/081 ,  H01P11/003 ,  H01L2221/68372 ,  H01L2223/6627 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19103

Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

公开(公告)号：US20210202397A1

公开(公告)日：2021-07-01

申请号：US17007945

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Doohwan Lee ,  Taeho Ko ,  Bongsoo Kim ,  Seokbong Park

IPC: H01L23/538 ,  H01L23/29 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01P3/08 ,  H01P11/00

Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

公开(公告)号：US20250054850A1

公开(公告)日：2025-02-13

申请号：US18786824

申请日：2024-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongsoo Kim ,  Chobi Kim ,  Pyunghwa Han

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a first substrate, a first semiconductor device disposed on the first substrate, a dummy substrate disposed on the first substrate, spaced apart from a side surface of the first semiconductor device, and surrounding the first semiconductor device, a core module disposed in the dummy substrate, and an encapsulant surrounding the first semiconductor device and in contact with the dummy substrate, wherein the core module includes a core wiring and a module substrate, the core module is disposed on the first substrate, and a side surface of the core module is surrounded by and spaced apart from an inner side surface of the dummy substrate, and the encapsulant is disposed between the dummy substrate and the side surface of the core module.

公开(公告)号：US20240030314A1

公开(公告)日：2024-01-25

申请号：US18175176

申请日：2023-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin SONG ,  Bongsoo Kim ,  Soojin Jeong

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/08 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L21/311 ,  H01L21/31155 ,  H01L29/0847 ,  H01L21/02107 ,  H01L29/42364

Abstract: A semiconductor device includes a substrate including an active pattern, a pair of channel patterns spaced apart from each other in a first direction on the active pattern, each of the pair of channel patterns including vertically stacked semiconductor patterns, a source/drain pattern between the pair of channel patterns, a pair of gate electrodes on the channel patterns, an active contact between the pair of gate electrodes, and outer spacers on side surfaces of the pair of gate electrodes. A distance between the outer spacers spaced apart from each other with the active contact therebetween is smaller than a width of the source/drain pattern in the first direction at a first level at which an upper surface of an uppermost semiconductor pattern among the semiconductor patterns is positioned.

公开(公告)号：US20230402518A1

公开(公告)日：2023-12-14

申请号：US18202085

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Kyujin Kim ,  Bongsoo Kim ,  Huijung Kim ,  Pyung Moon ,  Chulkwon Park ,  Gyunghyun Yoon ,  Heejae Chae

IPC: H01L29/423 ,  H10B12/00 ,  H01L29/49

CPC classification number: H01L29/4236 ,  H10B12/315 ,  H01L29/4916

Abstract: An integrated circuit (IC) device includes a gate trench formed inside a substrate, the gate trench including a bottom portion and a sidewall portion, a gate electrode structure disposed apart from the bottom portion and the sidewall portion of the gate trench, the gate electrode structure including a gate electrode including a first sub-gate electrode formed in a lower portion of the gate trench and a second sub-gate electrode formed on the first sub-gate electrode and a gate capping layer formed on the second sub-gate electrode, and a gate insulating layer formed between the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer formed between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure and a reinforcing insulating layer formed on a sidewall portion of the second sub-gate electrode.

公开(公告)号：US20220278049A1

公开(公告)日：2022-09-01

申请号：US17664132

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Doohwan Lee ,  Taeho Ko ,  Bongsoo Kim ,  Seokbong Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01P3/08 ,  H01P11/00 ,  H01L23/29

Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

公开(公告)号：US20220254787A1

公开(公告)日：2022-08-11

申请号：US17667697

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L27/108

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US20210351184A1

公开(公告)日：2021-11-11

申请号：US17384347

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US20210035983A1

公开(公告)日：2021-02-04

申请号：US16826655

申请日：2020-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoju Song ,  Seokhyun Kim ,  Youngjun Kim ,  Jinhyung Park ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

公开(公告)号：US20250016980A1

公开(公告)日：2025-01-09

申请号：US18629799

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Bongsoo Kim ,  Yongkwan Kim ,  Jongmin Kim ,  Taejin Park ,  Chansic Yoon ,  Jinwoo Han

IPC: H10B12/00

Abstract: A semiconductor device includes an active array in which a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction and crossing central portions of the active patterns; a bit line structure contacting first portions of the active patterns adjacent to a first sidewall of the gate structure and extending in a second direction; and a capacitor electrically connected to a second portion of each of the active patterns adjacent to a second sidewall of the gate structure. In a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction oblique with respect to the first direction. The active patterns arranged side by side in the second direction form an active column.