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公开(公告)号：US11735532B2
公开(公告)日：2023-08-22
申请号：US17664132
申请日：2022-05-19
发明人： Joonsung Kim , Doohwan Lee , Taeho Ko , Bongsoo Kim , Seokbong Park
IPC分类号： H01L23/538 , H01L23/31 , H01L23/66 , H01L23/00 , H01L25/065 , H01L25/10 , H01L21/683 , H01L21/48 , H01L21/56 , H01P3/08 , H01P11/00 , H01L23/29
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/295 , H01L23/3128 , H01L23/5383 , H01L23/5386 , H01L23/66 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/105 , H01P3/081 , H01P11/003 , H01L2221/68372 , H01L2223/6627 , H01L2224/214 , H01L2225/0651 , H01L2225/06568 , H01L2225/06586 , H01L2225/1035 , H01L2225/1058 , H01L2924/19032 , H01L2924/19041 , H01L2924/19103
摘要： A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.
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公开(公告)号：US20210202397A1
公开(公告)日：2021-07-01
申请号：US17007945
申请日：2020-08-31
发明人： Joonsung Kim , Doohwan Lee , Taeho Ko , Bongsoo Kim , Seokbong Park
IPC分类号： H01L23/538 , H01L23/29 , H01L23/31 , H01L23/66 , H01L23/00 , H01L25/065 , H01L25/10 , H01L21/683 , H01L21/48 , H01L21/56 , H01P3/08 , H01P11/00
摘要： A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.
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公开(公告)号：US20240030314A1
公开(公告)日：2024-01-25
申请号：US18175176
申请日：2023-02-27
发明人： Seungmin SONG , Bongsoo Kim , Soojin Jeong
IPC分类号： H01L29/66 , H01L29/40 , H01L21/311 , H01L21/3115 , H01L29/08 , H01L21/02 , H01L29/423
CPC分类号： H01L29/6656 , H01L29/401 , H01L21/311 , H01L21/31155 , H01L29/0847 , H01L21/02107 , H01L29/42364
摘要： A semiconductor device includes a substrate including an active pattern, a pair of channel patterns spaced apart from each other in a first direction on the active pattern, each of the pair of channel patterns including vertically stacked semiconductor patterns, a source/drain pattern between the pair of channel patterns, a pair of gate electrodes on the channel patterns, an active contact between the pair of gate electrodes, and outer spacers on side surfaces of the pair of gate electrodes. A distance between the outer spacers spaced apart from each other with the active contact therebetween is smaller than a width of the source/drain pattern in the first direction at a first level at which an upper surface of an uppermost semiconductor pattern among the semiconductor patterns is positioned.
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公开(公告)号：US20230402518A1
公开(公告)日：2023-12-14
申请号：US18202085
申请日：2023-05-25
发明人： Taejin Park , Kyujin Kim , Bongsoo Kim , Huijung Kim , Pyung Moon , Chulkwon Park , Gyunghyun Yoon , Heejae Chae
IPC分类号： H01L29/423 , H10B12/00 , H01L29/49
CPC分类号： H01L29/4236 , H10B12/315 , H01L29/4916
摘要： An integrated circuit (IC) device includes a gate trench formed inside a substrate, the gate trench including a bottom portion and a sidewall portion, a gate electrode structure disposed apart from the bottom portion and the sidewall portion of the gate trench, the gate electrode structure including a gate electrode including a first sub-gate electrode formed in a lower portion of the gate trench and a second sub-gate electrode formed on the first sub-gate electrode and a gate capping layer formed on the second sub-gate electrode, and a gate insulating layer formed between the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer formed between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure and a reinforcing insulating layer formed on a sidewall portion of the second sub-gate electrode.
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公开(公告)号：US20220278049A1
公开(公告)日：2022-09-01
申请号：US17664132
申请日：2022-05-19
发明人： Joonsung Kim , Doohwan Lee , Taeho Ko , Bongsoo Kim , Seokbong Park
IPC分类号： H01L23/538 , H01L23/31 , H01L23/66 , H01L23/00 , H01L25/065 , H01L25/10 , H01L21/683 , H01L21/48 , H01L21/56 , H01P3/08 , H01P11/00 , H01L23/29
摘要： A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.
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公开(公告)号：US20220254787A1
公开(公告)日：2022-08-11
申请号：US17667697
申请日：2022-02-09
发明人： Youngjun Kim , Seokhyun Kim , Jinhyung Park , Hoju Song , Hyeran Lee , Bongsoo Kim , Sungwoo Kim
IPC分类号： H01L27/108
摘要： A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.
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公开(公告)号：US20210351184A1
公开(公告)日：2021-11-11
申请号：US17384347
申请日：2021-07-23
发明人： Hyosub Kim , Keunnam Kim , Dongoh Kim , Bongsoo Kim , Euna Kim , Chansic Yoon , Kiseok Lee , Hyeonok Jung , Sunghee Han , Yoosang Hwang
IPC分类号： H01L27/108 , H01L23/528
摘要： A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.
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公开(公告)号：US20210035983A1
公开(公告)日：2021-02-04
申请号：US16826655
申请日：2020-03-23
发明人： Hoju Song , Seokhyun Kim , Youngjun Kim , Jinhyung Park , Hyeran Lee , Bongsoo Kim , Sungwoo Kim
IPC分类号： H01L27/108
摘要： A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.
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公开(公告)号：US11917815B2
公开(公告)日：2024-02-27
申请号：US18123736
申请日：2023-03-20
发明人： Hyosub Kim , Keunnam Kim , Dongoh Kim , Bongsoo Kim , Euna Kim , Chansic Yoon , Kiseok Lee , Hyeonok Jung , Sunghee Han , Yoosang Hwang
IPC分类号： H10B12/00 , H01L27/108 , H01L23/528
CPC分类号： H10B12/315 , H01L23/5283 , H10B12/053 , H10B12/34 , H10B12/482 , H10B12/485 , H10B12/488
摘要： A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.
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公开(公告)号：US11887971B2
公开(公告)日：2024-01-30
申请号：US17866598
申请日：2022-07-18
发明人： Bongsoo Kim
IPC分类号： H01L25/065 , H01L23/522 , H01L23/10 , H01L23/538
CPC分类号： H01L25/0657 , H01L23/10 , H01L23/5223 , H01L23/5384 , H01L23/5386
摘要： A semiconductor package includes; a lower connection structure, a semiconductor chip on the lower connection structure, an intermediate connection structure on the lower connection structure, a sealing layer covering the semiconductor chip, and an upper connection structure including a first upper insulating layer on the sealing layer, a first upper conductive pattern layer on the first upper insulating layer, and a first upper via penetrating the first upper insulating layer to directly connect the first upper conductive pattern layer to the intermediate connection structure. A height from an upper surface of the lower connection structure to an upper surface of the sealing layer is less than or equal to a maximum height from the upper surface of the lower connection structure to an upper surface of the intermediate connection structure.
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