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公开(公告)号：US11706910B2
公开(公告)日：2023-07-18
申请号：US17229942
申请日：2021-04-14
发明人： Hyosub Kim , Keunnam Kim , Manbok Kim , Soojeong Kim , Chulkwon Park , Seungbae Jeon , Yoosang Hwang
IPC分类号： H10B12/00
CPC分类号： H10B12/315 , H10B12/0335 , H10B12/053 , H10B12/34 , H10B12/482
摘要： Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.
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公开(公告)号：US11889682B2
公开(公告)日：2024-01-30
申请号：US17373539
申请日：2021-07-12
发明人： Taejin Park , Kyujin Kim , Chulkwon Park , Sunghee Han
IPC分类号： H10B12/00
CPC分类号： H10B12/50 , H10B12/0335 , H10B12/053 , H10B12/09 , H10B12/315 , H10B12/34 , H10B12/482
摘要： A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.
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公开(公告)号：US20230402518A1
公开(公告)日：2023-12-14
申请号：US18202085
申请日：2023-05-25
发明人： Taejin Park , Kyujin Kim , Bongsoo Kim , Huijung Kim , Pyung Moon , Chulkwon Park , Gyunghyun Yoon , Heejae Chae
IPC分类号： H01L29/423 , H10B12/00 , H01L29/49
CPC分类号： H01L29/4236 , H10B12/315 , H01L29/4916
摘要： An integrated circuit (IC) device includes a gate trench formed inside a substrate, the gate trench including a bottom portion and a sidewall portion, a gate electrode structure disposed apart from the bottom portion and the sidewall portion of the gate trench, the gate electrode structure including a gate electrode including a first sub-gate electrode formed in a lower portion of the gate trench and a second sub-gate electrode formed on the first sub-gate electrode and a gate capping layer formed on the second sub-gate electrode, and a gate insulating layer formed between the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer formed between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure and a reinforcing insulating layer formed on a sidewall portion of the second sub-gate electrode.
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公开(公告)号：US11889681B2
公开(公告)日：2024-01-30
申请号：US17720664
申请日：2022-04-14
发明人： Taejin Park , Taehoon Kim , Kyujin Kim , Chulkwon Park , Sunghee Han , Yoosang Hwang
IPC分类号： H10B12/00
CPC分类号： H10B12/34 , H10B12/053 , H10B12/315 , H10B12/482
摘要： An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.
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公开(公告)号：US20230309293A1
公开(公告)日：2023-09-28
申请号：US18327920
申请日：2023-06-02
发明人： HYOSUB KIM , Keunnam Kim , Manbok Kim , Soojeong Kim , Chulkwon Park , Seungbae Jeon , Yoosang Hwang
IPC分类号： H10B12/00
CPC分类号： H10B12/315 , H10B12/34 , H10B12/053 , H10B12/0335 , H10B12/482
摘要： Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.
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6.发明公开公开(公告)号：US20230337418A1
公开(公告)日：2023-10-19
申请号：US18211807
申请日：2023-06-20
发明人： Jaepil LEE , Chulkwon Park
IPC分类号： H10B12/00 , G11C11/4074 , G11C11/408 , G11C11/4091
CPC分类号： H10B12/50 , H10B12/315 , G11C11/4074 , G11C11/4085 , G11C11/4087 , G11C11/4091
摘要： A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit, which includes sub peripheral circuits that are disposed under each sub cell array. Each sub peripheral circuit includes a sense amplifier region, which includes a plurality of bitline sense amplifiers, and a rest circuit region, which includes other circuits. First-type bitline sense amplifiers, which are connected to first-type bitlines, are disposed in the sense amplifier region of each sub peripheral circuit, and the first-type bitlines are disposed above the sense amplifier region of each sub peripheral circuit. Second-type bitline sense amplifiers, which are connected to second-type bitlines, are disposed in the sense amplifier region of a neighboring sub peripheral circuit adjacent in the column direction to a first sub peripheral circuit of the sub peripheral circuit, and the second-type bitlines are disposed above the rest region of each sub peripheral circuit.
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公开(公告)号：US11600570B2
公开(公告)日：2023-03-07
申请号：US17097337
申请日：2020-11-13
发明人： Hyo-Sub Kim , Sohyun Park , Daewon Kim , Dongoh Kim , Eun A Kim , Chulkwon Park , Taejin Park , Kiseok Lee , Sunghee Han
IPC分类号： H01L23/535 , H01L21/768 , H01L27/108 , H01L23/532
摘要： A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.
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8.发明申请公开(公告)号：US20220344344A1
公开(公告)日：2022-10-27
申请号：US17720664
申请日：2022-04-14
发明人： Taejin Park , Taehoon Kim , Kyujin Kim , Chulkwon Park , Sunghee Han , Yoosang Hwang
IPC分类号： H01L27/108
摘要： An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.
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